Operating circuit having ESD protection function

An operating circuit coupled between an input/output pad and a ground terminal and comprising:

• a core circuit;
• a first N-type transistor determining whether to create an open circuit between the core circuit and the ground terminal according to a voltage level of a specific node;
• an electrostatic discharge (ESD) protection circuit coupled between the input/output pad and the core circuit to prevent an ESD current from passing through the core circuit and comprising:
• a detection circuit determining whether there is an ESD event at the input/output pad and generating a first detection signal according to the detection of the ESD event at the input/output pad;
• and
• a releasing element providing a release path according to the first detection signal to release the ESD current;
• and
• a control circuit controlling the voltage level of the specific node according to the first detection signal,
• wherein in response to the ESD event occurring at the input/output pad, the first N-type transistor is turned off to create the open circuit between the core circuit and the ground terminal such that the core circuit does not electrically couple to the ground terminal,
• wherein the core circuit comprises:
• a fuse;
• and
• an internal circuit, wherein in response to the internal circuit receiving a driving signal via the input/output pad, the internal circuit generates a current according to the driving signal, and in response to the current passing through the fuse, the fuse is programmed,
• wherein a source of the first N-type transistor is directly connected to the ground terminal,
• wherein the detection circuit further generates a second detection signal which is the opposite of the first detection signal,
• wherein the control circuit comprises:
• a first transistor setting the voltage level of the specific node to turn off the first N-type transistor in response to the ESD event occurring at the input/output pad;
• a second transistor coupled to the first transistor in parallel and setting the voltage level of the specific node according to the second detection signal;
• a third transistor coupled to the specific node and determining whether to transmit a specific signal to the specific node according to the second detection signal;
• and
• a fourth transistor coupled to the specific node and determining whether to transmit the specific signal to the specific node according to the first detection signal,
• wherein in response to the first transistor being turned on, the second transistor is also turned on, and in response to the first transistor being turned off, the second transistor is turned off, and
• wherein in response to the third transistor being turned on, the fourth transistor is also turned on, and in response to the third transistor being turned off, the fourth transistor is turned off.