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AssigneeAnalog Devices International Unlimited Company
InventorsJavier A. Salcedo, Srivatsan Parthasarathy, Enrique C. Bosch
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High voltage tolerant electrical overstress protection with low leakage current and low capacitance is provided. In one embodiment, a semiconductor die includes a signal pad, an internal circuit electrically connected to the signal pad, a power clamp electrically connected to an isolated node, and one or more isolation blocking voltage devices electrically connected between the signal pad and the isolated node. The one or more isolation blocking voltage devices are operable to isolate the signal pad from a capacitance of the power clamp. In another embodiment, a semiconductor die includes a signal pad, a ground pad, a high voltage/high speed internal circuit electrically connected to the signal pad, and a first thyristor and a second thyristor between the signal pad and the ground pad.
A semiconductor die with low leakage current and high voltage tolerant electrical overstress protection, the semiconductor die comprising:
A method of providing electrical overstress protection with low capacitance and low leakage current, the method comprising:
Dependencies are inferred from the claim text.