Magnetoelectric spin orbit logic based minority gate
AssigneeIntel Corporation
InventorsHuichu Liu, Tanay Karnik, Sasikanth Manipatruni, Daniel Morris, Kaushik Vaidyanathan, Ian Young
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Abstract
An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.
Claims20
An apparatus comprising:
- a magnet layer having a first portion and a second portion;
- a stack of layers, a portion of which is on the first portion of the magnet layer, wherein the stack of layers comprises spin orbit material;
- a layer on the second portion of the magnet layer, the layer comprising a magnetoelectric material;
- a conductor coupled to the layer;
- a first device coupled to the magnet, wherein the first device is controllable by a clock;
- a current mirror coupled to the first device and to a first supply node;
- and
- a second device coupled to a second supply node and to the stack of layers, wherein the second device is controllable by the clock.
An apparatus comprising:
- a first logic device comprising a spin orbit material, a magnetoelectric material, at least two transistors to operate using a first clock, and a current mirror coupled to one of the at least two transistors;
- a second logic device comprising a spin orbit coupling material, a magnetoelectric material, at least two transistors to operate using the first clock, and a current mirror coupled to one of the at least two transistors;
- a third logic device comprising a spin orbit coupling material, a magnetoelectric material, at least two transistors to operate using the first clock, and a current mirror coupled to one of the at least two transistors;
- and
- a fourth logic device coupled to the first, second and third logic devices, the fourth logic device comprising a spin orbit coupling material, a magnetoelectric material, at least two transistors to operate using a second clock, and a current mirror coupled to one of the at least two transistors, wherein the first and second clocks have different phases.
A system comprising:
- a memory;
- a processor coupled to the memory, wherein the processor comprises a minority logic gate comprising:
- a magnet having a first portion and a second portion;
- a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers comprises spin orbit material;
- a layer adjacent to the second portion, the layer comprising a magnetoelectric material;
- a conductor adjacent to the layer;
- a first device coupled to the magnet, wherein the first device is controllable by a clock;
- a current mirror coupled to the first device and to a first supply node;
- and
- a second device coupled to a second supply node and to a layer of the stack of layers, wherein the second device is controllable by the clock;
- and
- a wireless interface to allow the processor to communicate with another device.
Dependencies are inferred from the claim text.