Encapsulation layers of thin film transistors

A computing device comprising:

• a circuit board;
• and
• a memory device coupled to the circuit board and including a memory array, wherein the memory array includes a plurality of memory cells, a memory cell of the plurality of memory cells includes a transistor and a storage cell, and wherein the transistor includes:
• a substrate;
• a metallic encapsulation layer above the substrate, wherein the metallic encapsulation layer is a part of a word line for the memory array, and wherein the metallic encapsulation layer has a lateral width;
• a gate electrode above the metallic encapsulation layer;
• a channel layer above the gate electrode, wherein the channel layer includes a source area and a drain area, and wherein the channel layer has a lateral width the same as the lateral width of the metallic encapsulation layer;
• and
• a source electrode coupled to the source area, and a drain electrode coupled to the drain area, wherein the metallic encapsulation layer extends laterally beneath the source electrode and the drain electrode;
• and
• the storage cell is coupled to a bit line of the memory array.

A method for forming a semiconductor device, the method comprising:

• forming a metallic encapsulation layer above a substrate, the metallic encapsulation layer having a lateral width;
• forming a gate electrode above the metallic encapsulation layer;
• forming a channel layer above the gate electrode, wherein the channel layer includes a source area and a drain area, and wherein the channel layer has a lateral width the same as the lateral width of the metallic encapsulation layer;
• and
• forming a source electrode coupled to the source area, and a drain electrode coupled to the drain area, wherein the metallic encapsulation layer extends laterally beneath the source electrode and the drain electrode.