Semiconductor device and manufacturing method thereof

A semiconductor device including a p-type gate-all-around field effect transistor (GAA FET) and an n-type GAA FET both disposed over a semiconductor substrate, wherein:

• the p-type GAA FET includes:
• first semiconductor layers made of a first semiconductor material vertically arranged directly above a first bottom fin layer, the first bottom fin layer made of a second semiconductor material, continuously protruding from a substrate made of the second semiconductor material, and being embedded in an isolation insulating layer disposed on the substrate, a bottommost one of the first semiconductor layers being located above an upper surface of the isolation insulating layer, each of the first semiconductor layers having a first channel region and a first source/drain region adjacent to the first channel region;
• a first gate dielectric layer fully wrapping around the first channel region of each of the semiconductor layers;
• and
• a first source/drain region including a first epitaxial layer made of a third semiconductor material and fully wrapping around the first source/drain region of each of the first semiconductor layers,
• the n-type GAA FET includes:
• second semiconductor layers made of the first semiconductor material vertically arranged directly above a second bottom fin layer, the second bottom fin layer made of the second semiconductor material, continuously protruding from the substrate, and being embedded in the isolation insulating layer, a bottommost one of the second semiconductor layers being located above the upper surface of the isolation insulating layer, each of the second semiconductor layers having a second channel region;
• a second gate dielectric layer fully wrapping around the second channel region each of the second semiconductor layers;
• and
• a second source/drain region including a second epitaxial layer made of a fourth semiconductor material and third semiconductor layers vertically arranged, each of which contact the second gate dielectric layer and is fully wrapped around by the second epitaxial layer, wherein:
• the first semiconductor material is Si1-xGex, where 0.9≤x≤1.0,
• the second semiconductor material is Si1-yGey, where y<x and 0.3≤y≤0.7,
• the third semiconductor material is GeSn, and
• the fourth semiconductor material is SiC or Si1-zGez, where 0≤z≤0.3.

A semiconductor device including a gate-all-around field effect transistor (GAA FET), the GAA FET comprising:

• channel regions made of a first semiconductor material vertically arranged directly above a bottom fin layer, the bottom fin layer being made of a second semiconductor material, protruding from a substrate made of the second semiconductor material, and being embedded in an isolation insulating layer disposed on the substrate;
• a gate dielectric layer fully wrapping around each of the channel regions;
• and
• a source/drain region, wherein:
• a bottommost one of the channel regions is located above an upper surface of the isolation insulating layer,
• at least one of the channel regions has a greater channel length than at least one of other channel regions,
• the source/drain region includes:
• an epitaxial layer made of a third semiconductor material in contact with the channel regions;
• and
• a plurality of semiconductor layers made of a fourth semiconductor material, each of the plurality of semiconductor layers contacts the gate dielectric layer and is fully wrapped around by the epitaxial layer, and
• the first semiconductor material is Si1-xGex, and the second semiconductor material is Si1-yGey, where y<x, and
• the third semiconductor material is GeSn.