Transistor with a negative capacitance and a method of creating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsFeng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
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Abstract
The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
Claims20
A method, comprising:
- forming a fin on a substrate;
- forming a dielectric layer on the substrate, the fin extending through the dielectric layer;
- forming first and second spacers on the fin;
- forming a gate dielectric layer on the dielectric layer and on at least three sides of the fin;
- forming a ferroelectric layer on the gate dielectric layer, the ferroelectric layer being spaced from the fin and the first and second spacers by the gate dielectric layer;
- and
- forming a gate electrode on the ferroelectric layer.
A method, comprising:
- forming a first fin on a substrate, the first fin including a channel region having a first width;
- forming a second fin on the substrate, the second fin including a channel region having a second width;
- forming first and second spacers on the first fin;
- forming third and fourth spacers on the second fin;
- forming a first dielectric layer on at least three sides of the first fin and on at least three sides of the second fin;
- forming a ferroelectric layer on the first dielectric layer, the ferroelectric layer being spaced from the first fin and the first and second spacers by the first dielectric layer;
- and
- forming a second dielectric layer on the first dielectric layer, the ferroelectric layer being spaced from the second fin and the third and fourth spacers by the second dielectric layer.
A method, comprising:
- forming a fin on a substrate;
- forming first and second spacers on the fin;
- forming a gate dielectric layer on at least three sides of the fin and on the first and second spacers;
- forming a ferroelectric layer on the gate dielectric layer, the ferroelectric layer being spaced from the fin and the first and second spacers by the gate dielectric layer;
- and
- forming a gate electrode on the ferroelectric layer.
Dependencies are inferred from the claim text.