Ppower semiconductor device with anticorrosive edge termination structure

A power semiconductor device, comprising:

• a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge;
• an active region configured to conduct a load current between the first load terminal structure and the second load terminal structure in a conducting state of the power semiconductor device;
• an edge termination region separating the active region from the lateral chip edge;
• an insulation layer arranged at the front side, wherein a lateral edge of the insulation layer defines a contact hole, the contact hole being filled with a metal and/or polysilicon layer that is in contact with a doped semiconductor region of the semiconductor body;
• and
• a hard passivation layer that is formed from a hard passivation material and arranged at the front side at least in a portion of the edge termination region such that the hard passivation layer does not extend above the lateral edge of the insulation layer and the hard passivation layer at least partially covers the polysilicon and/or metal layer,
• wherein the contact hole is defined by a second lateral edge of the insulation layer that is opposite the lateral edge of the insulation layer, and
• wherein the power semiconductor device is configured such that no regions of the hard passivation material which at least partially cover the polysilicon and/or metal layer extend over the lateral edge or the second lateral edge.

A power semiconductor device, comprising:

• a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge;
• an active region configured to conduct a load current between the first load terminal structure and the second load terminal structure in a conducting state of the power semiconductor device;
• an edge termination region separating the active region from the lateral chip edge;
• a hard passivation layer arranged at the front side at least in a portion of the edge termination region, the hard passivation layer comprising an oxide layer having an oxide layer thickness;
• a metal layer arranged at the front side at least in a portion of the edge termination region and having a lateral edge;
• and
• an insulation layer arranged at the front side at least in a portion of the edge termination region,
• wherein a lateral edge of the insulation layer is covered by the metal layer,
• wherein in a cross-section along a vertical direction pointing from the front side to the backside, the cross-section is perpendicular to the lateral edge and a common lateral extension range of the hard passivation layer and the metal layer amounts to at most 10 times the oxide layer thickness,
• wherein the common lateral extension range does not extend across any lateral edge of the insulation layer within the edge termination region.