Structure providing charge controlled electronic fuse

A laterally-diffused metal-oxide semiconductor (LDMOS) device, comprising:

• a first source/drain region and a second source/drain region in a semiconductor body;
• a trench isolation between the first and second source/drain regions in the semiconductor body;
• a p-well about the first source/drain region;
• an n-well about the second source/drain region, creating a source/drain extension adjacent the trench isolation within the n-well;
• an n-type doped charge trap section adjacent to the p-well and extending partially into the source/drain extension;
• and
• a gate conductor of a gate structure over the trench isolation and the p-well, the n-well, and the n-type doped charge trap section,
• wherein a portion of the n-well is between the trench isolation and the n-type doped charge trap section, and
• wherein the semiconductor body includes a fin over a bulk substrate.

An electronic fuse, comprising:

• a first source/drain region and a second source/drain region in a semiconductor body;
• a trench isolation between the first and second source/drain regions in the semiconductor body;
• an n-well about the first source/drain region;
• a p-well about the second source/drain region, creating a source/drain extension adjacent the trench isolation within the p-well;
• a p-type doped charge trap section adjacent to the n-well and extending partially into the source/drain extension;
• and
• a gate conductor of a gate structure over the trench isolation and the n-well, the p-well, and the p-type doped charge trap section,
• wherein a dopant concentration of the p-type doped charge trap section is at least twice that of the p-well.