Semiconductor devices and methods of manufacturing thereof

A semiconductor device, comprising:

• a plurality of semiconductor layers vertically separated from one another, wherein each of the plurality of semiconductor layers extends along a first lateral direction;
• a gate structure that extends along a second lateral direction, wherein the gate structure comprises a plurality of first gate sections and a plurality of second gate sections, and wherein the plurality of first gate sections are laterally aligned with the plurality of semiconductor layers, respectively, and the plurality of second gate sections are each vertically disposed between adjacent ones of the plurality of semiconductor layers;
• and
• an inner spacer comprising a first group and a second group;
• wherein each of the first group of the inner spacer contacts an end of a corresponding one of the plurality of first gate sections in a first curvature-based profile, and each of the second group of the inner spacer contacts an end of a corresponding one of the plurality of second gate sections in a second curvature-based profile.

A method for making a semiconductor device, comprising:

• forming a fin structure extending along a first lateral direction, wherein the fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on top of one another;
• forming a connected layer overlaying the fin structure;
• forming a dummy gate structure over a portion of the fin structure with the connected layer disposed between the dummy gate structure and the fin structure, wherein the dummy gate structure extends along a second lateral direction perpendicular to the first lateral direction;
• removing portions of the fin structure that are not overlaid by the dummy gate structure;
• etching, along the first lateral direction, respective end portions of each of the first semiconductor layers, respective end portions of at least lower portions of the dummy gate structure, and end portions of the connected layer, wherein a respective remaining portion of each of the first semiconductor layers and a respective remaining portion of each of the lower portions of the dummy gate structure each present a curvature-based profile;
• forming inner spacers that fill the etched end portions of the first semiconductor layers and the etched end portions of the dummy gate structure;
• and
• replacing respective remaining portions of the first semiconductor layers and the dummy gate structure with an active gate structure.