Methods for forming planar metal-oxide-semiconductor field-effect transistors

A non-transitory, computer readable medium having instructions stored thereon that, when executed, cause a method for forming a planar silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) to be performed, the method comprising:

• depositing a first dielectric layer on a substrate;
• depositing a hardmask layer on the substrate;
• forming a first gate dielectric portion of the planar SiC MOSFET in the first dielectric layer on the substrate by patterning and etching the hardmask layer, wherein a hardmask portion remains on the first gate dielectric portion and wherein a first thickness of the first gate dielectric portion is configured to reduce a gate-drain capacitance of the planar SiC MOSFET;
• depositing a first spacer layer with a second thickness on the substrate;
• implanting a P-well of the planar SiC MOSFET in the substrate;
• depositing a second spacer layer on the substrate;
• forming a second spacer surrounding the first gate dielectric portion and the hardmask portion on the substrate;
• implanting an N+ source of the planar SiC MOSFET in the substrate;
• removing the first spacer layer, the second spacer, and the hardmask portion to reveal the first gate dielectric portion on the substrate;
• forming a second gate dielectric portion of the planar SiC MOSFET with a third thickness on the substrate;
• and
• forming a gate of the planar SiC MOSFET on the substrate.