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US 11,387,336 B2Granted
Drain and/or gate interconnect and finger structure
AssigneeWolfspeed, Inc.
InventorsFrank Trang, Zulhazmi Mokhti, Haedong Jang
Life of this patent
Estimating the term…
Abstract
Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect.
Claims20
A transistor device, comprising:
- a semiconductor structure;
- a gate finger extending on the semiconductor structure in a first direction;
- a gate interconnect extending on the semiconductor structure in the first direction, the gate interconnect having a first end and a second end;
- a first conductive via coupled between the gate interconnect and the gate finger;
- and
- a second conductive via coupled to the gate interconnect at an interior position of the gate interconnect that is offset from the first and second ends of the gate interconnect,
- wherein the second conductive via connects to an upper side of the gate interconnect and the first conductive via connects to a lower side of the gate interconnect.
4 more elements
A transistor device, comprising:
- a semiconductor structure;
- a gate finger extending on the semiconductor structure in a first direction, the gate finger comprising a first segment and a second segment;
- and
- a gate runner extending on the semiconductor structure and configured to provide a gate signal symmetrically to the first segment and the second segment of the gate finger.
1 more element
A transistor device, comprising:
- a semiconductor structure comprising a source region and a drain region;
- a gate finger extending on the semiconductor structure in a first direction between the source region and the drain region;
- a gate interconnect extending on the semiconductor structure in the first direction and connected to the gate finger;
- and
- a gate runner extending on the semiconductor structure in the first direction and connected to the gate interconnect at an interior position that is offset from first and second ends of the gate interconnect.
2 more elements
Dependencies are inferred from the claim text.