Source/drain contact structure

A semiconductor structure, comprising:

• a first source/drain feature and a second source/drain feature;
• a channel region disposed between the first source/drain feature and the second source/drain feature;
• a metal gate structure disposed directly over the channel region;
• a first dielectric layer disposed directly over the metal gate structure;
• a second dielectric layer disposed directly over the first source/drain feature;
• a third dielectric layer disposed directly over the second dielectric layer;
• a source/drain contact disposed directly over the second source/drain feature;
• a first gate spacer extending between the metal gate structure and the second dielectric layer, the first dielectric layer and the second dielectric layer, and the first dielectric layer and the third dielectric layer, wherein a top surface of the first dielectric layer is higher than a top surface of the second dielectric layer;
• a second gate spacer extending between the metal gate structure and the source/drain contact and between the source/drain contact and the first dielectric layer;
• and
• a contact etch stop layer disposed between the second dielectric layer and the first source/drain feature, between the second dielectric layer and the first gate spacer, between the third dielectric layer and the first gate spacer, and between the third dielectric layer and the first dielectric layer.

A semiconductor structure, comprising:

• a source/drain feature disposed over a source/drain region of an active region;
• a gate structure disposed over a channel region of the active region, the channel region being adjacent the source/drain region;
• a first dielectric layer disposed directly over the gate structure;
• a second dielectric layer disposed directly over the source/drain feature;
• a third dielectric layer disposed directly over and in contact with a top surface of the second dielectric layer;
• and
• a gate spacer extending between the gate structure and the second dielectric layer, the first dielectric layer and the second dielectric layer, and the first dielectric layer and the third dielectric layer,
• wherein the second dielectric layer comprises silicon oxide or a low-k dielectric material,
• wherein the third dielectric layer comprises silicon nitride, silicon, silicon carbide, silicon oxycarbonitride, or silicon carbonitride,
• wherein a bottom surface of the third dielectric layer is lower than a top surface of the gate spacer.