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US 11,387,329 B2Granted
Tri-gate architecture multi-nanowire confined transistor
AssigneeIntel Corporation
InventorsHan Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul Fischer, Walid Hafez
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Abstract
Transistor structures including a fin structure having multiple graded III-N material layers with polarization layers therebetween, integrated circuits including such transistor structures, and methods for forming the transistor structures are discussed. The transistor structures further include a source, a drain, and a gate coupled to the fin structure. The fin structure provides a multi-gate multi-nanowire confined transistor architecture.
Claims20
A transistor structure comprising:
- a fin structure comprising first and second graded group III-nitride (III-N) material layers with a polarization layer therebetween, the first graded III-N material layer comprising first and second group III constituents, wherein the first graded III-N material layer comprises a graded first group III constituent concentration profile with a decreasing concentration of the first group III constituent along a height of the fin structure;
- a source and a drain coupled to the fin structure;
- and
- a gate between the source and the drain and coupled to the fin structure.
1 more element
A system comprising:
- a memory;
- and
- an integrated circuit coupled to the memory, the integrated circuit comprising a transistor structure comprising:
- a fin structure comprising first and second graded group III-nitride (III-N) material layers with a polarization layer therebetween, the first graded III-N material layer comprising first and second group III constituents, wherein the first graded III-N material layer comprises a graded first group III constituent concentration profile with a decreasing concentration of the first group III constituent along a height of the fin structure;
- a source and a drain coupled to the fin structure;
- and
- a gate between the source and the drain and coupled to the fin structure.
4 more elements
A method of forming a transistor structure comprising:
- growing, over a substrate, a first graded III-N material layer, a polarization layer, and a second graded III-N material layer, wherein the polarization layer is between the first and second graded III-N material layers, the first graded III-N material layer comprises first and second group III constituents, and the first graded III-N material layer comprises a graded first group III constituent concentration profile with a decreasing concentration of the first group III constituent along a height extending from the substrate;
- patterning the first graded III-N material layer, the polarization layer, and the second graded III-N material layer to form a fin structure;
- forming a gate coupled to the fin structure;
- and
- forming a source and a drain coupled to the fin structure, wherein the gate is between the source and the drain.
2 more elements
Dependencies are inferred from the claim text.