Vertical semiconductor device with enhanced contact structure and associated methods

A vertical semiconductor device comprising:

• a semiconductor substrate having at least one trench therein;
• a superlattice liner at least partially covering sidewall portions of the at least one trench, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions;
• a semiconductor layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner;
• and
• a conductive body within the at least one trench defining a source contact and comprising
• a metal liner adjacent the semiconductor layer and comprising titanium, and
• a tungsten body adjacent the metal liner and filling the at least one trench.

A vertical semiconductor device comprising:

• a semiconductor substrate having at least one trench therein;
• a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer, with each at least one oxygen monolayer of each group of layers being constrained within a crystal lattice of adjacent base silicon portions;
• a semiconductor layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner;
• and
• a conductive body within the at least one trench defining a source contact.

A vertical semiconductor device comprising:

• a semiconductor substrate having at least one trench therein;
• a superlattice liner at least partially covering sidewall portions of the at least one trench, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions;
• a semiconductor layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner;
• and
• a conductive body within the at least one trench defining a source contact and comprising a metal liner adjacent the semiconductor layer and comprising a first metal, and a metal body adjacent the metal liner, filling the at least one trench and comprising a second metal.

A method for making a vertical semiconductor device comprising:

• forming at least one trench in a semiconductor substrate;
• forming a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions;
• forming a semiconductor layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner;
• and
• forming a conductive body within the at least one trench defining a source contact.