US 11,387,320 B2Granted

Transistors with high concentration of germanium

AssigneeIntel Corporation

InventorsAnand S. Murthy, Glenn A. Glass, Tahir Ghani, Ravi Pillarisetty, Niloy Mukherjee, Jack T. Kavalieros, Roza Kotlyar, Willy Rachmady, Mark Y. Liu

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Abstract

Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

Claims20

Dependent claims

An integrated circuit structure, comprising:

a fin comprising silicon
a gate electrode over the fin, the gate electrode having a first side, and the gate electrode having a second side opposite the first side;
a first dielectric spacer along the first side of the gate electrode;
a first source or drain region in the fin proximate the first side of the gate electrode, a portion of the first source or drain region beneath the first dielectric spacer, and the first source or drain region comprising two or more facets and a top surface, wherein the first source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%, and wherein the first source or drain region comprises a boron concentration in excess of 1E20;
a first layer over the top surface of the first source or drain region, the first layer comprising silicon, germanium and titanium;
a second dielectric spacer along the second side of the gate electrode;
a second source or drain region in the fin proximate the second side of the gate electrode, a portion of the second source or drain region beneath the second dielectric spacer, and the second source or drain region comprising two or more facets and a top surface, wherein the second source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%, and wherein the second source or drain region comprises a boron concentration in excess of 1E20;
and
a second layer over the top surface of the second source or drain region, the second layer comprising silicon, germanium and titanium.

6 more elements

An integrated circuit structure, comprising:

a body comprising silicon;
a gate electrode over the body, the gate electrode having a first side, and the gate electrode having a second side opposite the first side;
a first dielectric spacer along the first side of the gate electrode;
a first source or drain region in the body proximate the first side of the gate electrode, a portion of the first source or drain region beneath the first dielectric spacer, and the first source or drain region comprising two or more facets and a top surface, wherein the first source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%, and wherein the first source or drain region comprises a boron concentration in excess of 1E20;
a first layer over the top surface of the first source or drain region, the first layer comprising silicon, germanium and titanium;
a second dielectric spacer along the second side of the gate electrode;
a second source or drain region in the body proximate the second side of the gate electrode, a portion of the second source or drain region beneath the second dielectric spacer, and the second source or drain region comprising two or more facets and a top surface, wherein the second source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%, and wherein the second source or drain region comprises a boron concentration in excess of 1E20;
and
a second layer over the top surface of the second source or drain region, the second layer comprising silicon, germanium and titanium.

6 more elements

An integrated circuit structure, comprising:

a fin comprising silicon;
a gate electrode over the fin, the gate electrode having a first side, and the gate electrode having a second side opposite the first side;
a first dielectric spacer along the first side of the gate electrode;
a first layer above the fin and proximate the first dielectric spacer, the first layer comprising silicon, germanium and titanium;
a first semiconductor region between the first layer and the fin, a portion of the first semiconductor region beneath the first dielectric spacer, and the first semiconductor region comprising two or more facets and a top surface, wherein a first region of the first semiconductor region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%, and wherein a second region of the first semiconductor region comprises a boron concentration in excess of 1E20;
a second dielectric spacer along the second side of the gate electrode;
a second layer above the fin and proximate the second dielectric spacer, the second layer comprising silicon, germanium and titanium;
and
a second semiconductor region between the second layer and the fin, a portion of the second semiconductor region beneath the second dielectric spacer, and the second semiconductor region comprising two or more facets and a top surface, wherein a first region of the second semiconductor region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%, and wherein a second region of the second semiconductor region comprises a boron concentration in excess of 1E20.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/707,490Filed 9 Dec 2019 · continuation
Priority: 21 Dec 2010
Published: US 2020/0144362 A17 May 2020
Granted: 12 Jul 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification48 codes

H10D 62/122
Nanowire, nanosheet or nanotube semiconductor bodies: oriented at angles to substrates, e.g. perpendicular to substrates
H10D 30/019
Manufacture or treatment: of FETs having stacked nanowire, nanosheet or nanoribbon channels
H10D 30/021
Manufacture or treatment: of FETs having insulated gates [IGFET]
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…

Family

Application12/975,278Parent of this continuation · filed 21 Dec 2010
Application14/535,387Parent of this continuation · filed 7 Nov 2014
US 8,901,537 B2Parent of this continuation · filed 2 Dec 2014
Application15/489,569Parent of this continuation · filed 17 Apr 2017
US 9,637,384 B2Parent of this continuation · filed 18 Apr 2017
US 2020/0144362 A1Pre-grant publication · published 7 May 2020
US 2012/0153387 A1Published application
US 2015/0060945 A1Published application
US 2017/0221724 A1Published application
US 9,627,384 B2Related patent
US 11,387,320 B2This patent

From the US filing history. Foreign family members aren’t listed.