Display panel and display apparatus

A display panel, comprising:

• a substrate which comprises a substrate display region corresponding to a display panel display region and a substrate non-display region corresponding to a display panel non-display region;
• a non-display region circuit which is located at the substrate non-display region;
• a packaging layer which is located on the non-display region circuit and has an area at least partially overlapping with the non-display region circuit;
• wherein the non-display region circuit comprises:
• a first conductive pattern which comprises at least one second through-hole;
• at least one buffer layer which is located at a side of the first conductive pattern close to the substrate;
• at least one gate insulating layer which is configured to electrically insulate the first conductive pattern and other conductive patterns;
• and
• at least one interlayer insulating layer which is located at a side of the first conductive pattern away from the substrate,
• the at least one gate insulating layer comprises a first gate insulating layer which is located at a side of the first conductive pattern away from the substrate;
• and
• portions of the at least one interlayer insulating layer and the first gate insulating layer at a position corresponding to the at least one second through-hole of the first conductive pattern are removed, so that the packaging layer is able to be in contact with at least one of the at least one buffer layer through the at least one second through-hole.

A display panel comprising:

• a substrate which comprises a substrate display region corresponding to a display panel display region and a substrate non-display region corresponding to a display panel non-display region;
• a non-display region circuit which is located at the substrate non-display region;
• a packaging layer which is located on the non-display region circuit and has an area at least partially overlapping with the non-display region circuit;
• a display region circuit located at the substrate display region, wherein the display region circuit comprises a thin film transistor which comprises a gate, a source, a drain and an active layer, and
• a display device which is located at the substrate display region, wherein the display device comprises a plurality of pixel units and a pixel defining layer, each of the plurality of pixel units comprises a first electrode electrically connected to the thin film transistor, and the pixel defining layer is configured to define the plurality of pixel units,
• wherein the non-display region circuit comprises:
• a first conductive pattern;
• at least one buffer layer which is located at a side of the first conductive pattern close to the substrate;
• at least one gate insulating layer which is configured to electrically insulate the first conductive pattern and other conductive patterns;
• and
• at least one interlayer insulating layer which is located at a side of the first conductive pattern away from the substrate,
• the first conductive pattern and the gate are located at a same layer and have same material, and
• the non-display region circuit further comprises a peripheral wiring, a first electrode pattern and a pixel defining pattern which are located on the interlayer insulating layer, wherein the peripheral wiring comprises a VSS power line, the first electrode pattern and the first electrode are located at a same layer and have same material, and the pixel defining pattern and the pixel defining layer are located at a same layer and have same material,
• an end of the peripheral wiring close to an outer edge of the display panel is closer to the outer edge of the display panel than an end of the pixel defining pattern close to the outer edge of the display panel;
• another end of the peripheral wiring away from the outer edge of the display panel is substantially flush with another end of the pixel defining pattern away from the outer edge of the display panel;
• and
• the first electrode pattern is electrically connected to the peripheral wiring.

A display panel comprising:

• a substrate which comprises a substrate display region corresponding to a display panel display region and a substrate non-display region corresponding to a display panel non-display region;
• a non-display region circuit which is located at the substrate non-display region;
• a packaging layer which is located on the non-display region circuit and has an area at least partially overlapping with the non-display region circuit;
• a display region circuit located at the substrate display region, wherein the display region circuit comprises a thin film transistor which comprises a gate, a source, a drain and an active layer, and
• a display device which is located at the substrate display region, wherein the display device comprises a plurality of pixel units and a pixel defining layer, each of the plurality of pixel units comprises a first electrode electrically connected to the thin film transistor, and the pixel defining layer is configured to define the plurality of pixel units,
• wherein the non-display region circuit comprises:
• a first conductive pattern;
• at least one buffer layer which is located at a side of the first conductive pattern close to the substrate;
• at least one gate insulating layer which is configured to electrically insulate the first conductive pattern and other conductive patterns;
• and
• at least one interlayer insulating layer which is located at a side of the first conductive pattern away from the substrate,
• the first conductive pattern and the gate are located at a same layer and have same material, and
• the non-display region circuit further comprises a peripheral wiring, a first electrode pattern and a pixel defining pattern which are located on the interlayer insulating layer, wherein the peripheral wiring comprises a VSS power line, the first electrode pattern and the first electrode are located at a same layer and have same material, and the pixel defining pattern and the pixel defining layer are located at a same layer and have same material,
• an end of the peripheral wiring close to an outer edge of the display panel is closer to the outer edge of the display panel than an end of the pixel defining pattern close to the outer edge of the display panel;
• another end of the pixel defining pattern away from the outer edge of the display panel is farther away from the outer edge of the display panel than another end of the peripheral wiring away from the outer edge of the display panel;
• and
• the first electrode pattern is electrically connected to the peripheral wiring.