Semiconductor device

A semiconductor device, comprising:

• a logic cell formed on a substrate and that includes a PMOSFET area and an NMOSFET area on the substrate, the PMOSFET and NMOSFET areas being spaced apart from each other in a first horizontal direction;
• a separation structure on at least one side of the logic cell, the separation structure extending in the first horizontal direction and separating the logic cell from an adjacent logic cell;
• a plurality of first connection lines in a first interlayer dielectric layer on the logic cell, the first connection lines extending parallel to each other in a second horizontal direction that intersects the first horizontal direction;
• and
• a plurality of second connection lines in a second interlayer dielectric layer on the first interlayer dielectric layer, the second connection lines extending parallel to each other in the first horizontal direction,
• wherein the plurality of first connection lines are at a second vertical level between a first vertical level at which the substrate is disposed and a third vertical level at which the plurality of second connection lines are disposed,
• wherein the first connection lines include:
• a first lower power line that extends horizontally along a first cell boundary of the logic cell;
• and
• a second lower power line that extends horizontally along a second cell boundary of the logic cell,
• wherein the first cell boundary is opposite in the first horizontal direction to the second cell boundary, and
• wherein the second connection lines include a first upper power line that vertically overlaps the separation structure, and
• wherein the first upper power line is electrically connected to at least one of the first lower power line and the second lower power line.

A semiconductor device, comprising:

• a logic cell on a substrate, the logic cell including a first active region and a second active region that are spaced apart from each other in a first horizontal direction;
• a first active pattern and a second active pattern on the first active region and the second active region, respectively, the first and second active patterns each extending in a second horizontal direction that intersects the first horizontal direction;
• a device isolation layer that covers lower sidewalls of the first active pattern and lower sidewalls of the second active pattern, an upper portion of each of the first and second active patterns vertically protruding beyond a top surface of the device isolation layer;
• a first source/drain pattern and a second source/drain pattern on the upper portion of the first active pattern and the upper portion of the second active pattern, respectively;
• a plurality of gate electrodes that extend in the first horizontal direction and run across the first and second active patterns;
• a plurality of first connection lines in a first interlayer dielectric layer on the gate electrodes;
• and
• a plurality of second connection lines in a second interlayer dielectric layer on the first interlayer dielectric layer, the second connection lines extending parallel to each other in the first horizontal direction, and the first interlayer dielectric layer being vertically between the second interlayer dielectric layer and the substrate,
• wherein the logic cell has a first cell boundary and a second cell boundary that extend in the second horizontal direction, the first cell boundary and the second cell boundary being opposite to each other in the first horizontal direction,
• wherein the first connection lines include:
• a first lower power line that extends horizontally along the first cell boundary;
• and
• a second lower power line that extends horizontally along the second cell boundary,
• wherein the second connection lines include:
• a first upper power line that vertically overlaps a first gate electrode of the gate electrodes;
• and
• an upper line that is offset in the second horizontal direction from each of the gate electrodes, when viewed in plan view,
• wherein the first upper power line is electrically connected to at least one of the first lower power line and the second lower power line,
• wherein the upper line extends from the first active region to the second active region, and
• wherein the upper line does not extend outward beyond the first cell boundary or the second cell boundary.