Memory cell and methods thereof
AssigneeFerroelectric Memory GmbH
InventorMarko Noack
Life of this patent
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Abstract
According to various aspects, a memory cell comprise: a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal to control the memory cell; a first memory element (FeFET1) and a second memory element (FeFET2), the first memory element comprising a first capacitive memory structure electrically connected to the first terminal and a first field-effect transistor structure coupled to the first capacitive memory structure and electrically connected to the third terminal and the forth terminal; the second memory element comprising a second capacitive memory structure electrically connected to the second terminal and a second field-effect transistor structure coupled to the second capacitive memory structure and electrically connected to the third terminal and the fifth terminal.
Claims20
A memory cell comprising:
- a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal to control the memory cell;
- a first memory element and a second memory element;
- the first memory element comprising a first capacitive memory structure electrically connected to the first terminal and a first field-effect transistor structure coupled to the first capacitive memory structure and electrically connected to the third terminal and the fourth terminal;
- the second memory element comprising a second capacitive memory structure electrically connected to the second terminal and a second field-effect transistor structure coupled to the second capacitive memory structure and electrically connected to the third terminal and the fifth terminal.
A memory cell comprising:
- a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal to control the memory cell;
- a first ferroelectric memory element and a second ferroelectric memory element,
- the first ferroelectric memory element comprising a first capacitive memory structure electrically connected to the first terminal and a first field-effect transistor structure coupled to the first capacitive memory structure and electrically connected to the third terminal and the fourth terminal;
- the second ferroelectric memory element comprising a second capacitive memory structure electrically connected to the second terminal and a second field-effect transistor structure coupled to the second capacitive memory structure and electrically connected to the third terminal and the fifth terminal.
A method of forming a memory cell, the method comprising:
- forming a first memory element and a second memory element;
- and
- forming a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal to control the memory cell;
- the first memory element comprising a first capacitive memory structure electrically connected to the first terminal and a first field-effect transistor structure coupled to the first capacitive memory structure and electrically connected to the third terminal and the fourth terminal;
- the second memory element comprising a second capacitive memory structure electrically connected to the second terminal and a second field-effect transistor structure coupled to the second capacitive memory structure and electrically connected to the third terminal and the fifth terminal.
Dependencies are inferred from the claim text.