US 11,387,251 B2Granted

Memory device

AssigneeKioxia Corporation

InventorsShigeki Kobayashi, Toru Matsuda, Hanae Ishihara

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Abstract

A memory device includes a substrate, first, second, and third conductive layers, a stack of fourth conductive layers, a memory pillar, and an insulator. The first, second, and third conductive layer are provided above the substrate. The stack of fourth conductive layers is provided above the third conductive layer. The memory pillar extends in the thickness direction through the stack and the third conductive layer and into the second conductive layer in a first region of the memory device. The insulator extends in a thickness direction through the stack, the third conductive layer, and the second conductive layer in a second region of the memory device. The insulator also extends in a second surface direction of the substrate. A thickness of the third conductive layer in a region through which the insulator extends is greater than a thickness of the third conductive layer in the first region.

Claims17

Dependent claims

A memory device comprising:

a substrate;
a first semiconductor layer provided above the substrate and including a first region having a first impurity concentration, a second region having a second impurity concentration above the first region, and a third region having a third impurity concentration above the second region, the second impurity concentration being higher than the first impurity concentration and the third impurity concentration;
a stacked body provided above the first semiconductor layer and including a plurality of first conductive layers stacked in a first direction;
a memory pillar extending in the first direction through the stacked body and the first semiconductor layer and having a side wall portion that is in contact with the second region of the first semiconductor layer;
a plurality of memory cells provided at intersections of the memory pillar and the plurality of first conductor layers;
an insulator extending in the first direction through the stacked body and the first semiconductor layer and in a second direction, and dividing the stacked body and the first semiconductor layer in a third direction, the second direction crossing the first direction, the third direction crossing the first direction and the second direction;
and
a first insulating layer provided between a side surface of the insulator and the first, second and third regions, the first insulating layer including a portion protruding into the second region in the third direction, wherein
the third region includes a first portion that is in contact with the insulator and a second portion that is in contact with the memory pillar, and
a thickness of the first portion in the first direction is greater than a thickness of the second portion in the first direction.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/800,214Filed 25 Feb 2020
Priority: JP JP2019-16936518 Sep 2019
Published: US 2021/0082947 A118 Mar 2021
Granted: 12 Jul 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10D 62/80
Semiconductor bodies, or regions thereof, of devices having potential barriers: characterised by the materials