Non-silicon N-Type and P-Type stacked transistors for integrated circuit devices

An integrated circuit (IC) device, comprising:

• a processor core;
• and
• a memory coupled to the processor core, wherein the processor core comprises a first transistor stacked with a second transistor, and wherein:
• the first transistor comprises a first source and a first drain coupled to a first channel material, wherein the first channel material comprises Ge, and the first source and the first drain have P-type conductivity;
• the second transistor comprises a second source and a second drain coupled to a second channel material, wherein the second channel material comprises an alloy of one or more Group III elements and one or more Group V elements, and the second source and the second drain have N-type conductivity;
• a gate electrode is adjacent to a sidewall of the first and second channel materials;
• and
• a gate dielectric is between the gate electrode and the sidewall of the first and second channel materials.

A method of fabricating an integrated circuit (IC) device structure, the method comprising:

• forming a multi-layered material stack comprising a plurality of first and second semiconductor material layers, wherein the first semiconductor material layers comprise Ge and the second semiconductor material layers comprise an alloy of one or more Group III elements and one or more Group V elements;
• forming a gate stack over the material stack, wherein the gate stack comprises a gate electrode and a gate dielectric;
• forming a P-type source and a P-type drain on opposite sides of the gate stack and in contact with a first layer of the material stack;
• forming an N-type source and an N-type drain on opposite sides of the gate stack and in contact with a second layer of the material stack;
• forming a first terminal contact to one or more of the P-type source and N-type source;
• and
• forming a second terminal contact to one of one or more of the P-type drain and N-type drain.