Semiconductor device

A semiconductor device comprising:

• a substrate comprising a first active region and a second active region;
• a first active pattern and a second active pattern on the first and second active regions, respectively;
• a pair of first source/drain patterns, a semiconductor pattern, and a first channel pattern between the pair of first source/drain patterns, wherein the pair of first source/drain patterns, the semiconductor pattern, and the first channel pattern are in an upper portion of the first active pattern;
• a pair of second source/drain patterns and a second channel pattern between the pair of second source/drain patterns, wherein the pair of second source/drain patterns and the second channel pattern are in an upper portion of the second active pattern;
• first and second gate electrodes intersecting the first and second channel patterns, respectively;
• a first gate dielectric pattern between the first gate electrode and the first channel pattern;
• and
• a second gate dielectric pattern between the second gate electrode and the second channel pattern,
• wherein the first channel pattern and the second channel pattern each comprise germanium (Ge),
• wherein a first concentration of germanium (Ge) of the first channel pattern is different from a second concentration of germanium (Ge) of the second channel pattern,
• wherein a top of the first channel pattern is at a first vertical level,
• wherein bottoms of the pair of first source/drain patterns are at a second vertical level, and
• wherein the first concentration of germanium (Ge) in the first channel pattern gradually increases from the first vertical level toward the second vertical level.

A semiconductor device comprising:

• a substrate comprising a PMOSFET region and an NMOSFET region spaced apart from each other in a first direction;
• a first active pattern and a second active pattern on the PMOSFET region and the NMOSFET region, respectively, the first and second active patterns extending in a second direction intersecting the first direction, wherein an upper portion of the first active pattern comprises a semiconductor pattern;
• a device isolation layer on the substrate that extends over a sidewall of a lower portion of each of the first and second active patterns, wherein an upper portion of each of the first and second active patterns protrudes upward from a top surface of the device isolation layer;
• a pair of first source/drain patterns in the upper portion of the first active pattern;
• a pair of second source/drain patterns in the upper portion of the second active pattern;
• a gate electrode intersecting the first and second active patterns and extending in the first direction;
• a gate dielectric pattern between the gate electrode and the first and second active patterns;
• active contacts electrically connected to the first and second source/drain patterns;
• and
• interconnection lines on the active contacts and electrically connected to the active contacts and the gate electrode,
• wherein the semiconductor pattern of the first active pattern comprises silicon-germanium (SiGe),
• wherein the semiconductor pattern of the first active pattern further comprises nitrogen (N) as an impurity,
• wherein a concentration of germanium (Ge) in the semiconductor pattern increases from a top surface of the semiconductor pattern toward a bottom surface of the semiconductor pattern, and
• wherein a concentration of nitrogen (N) in the semiconductor pattern decreases from the top surface of the semiconductor pattern toward the bottom surface of the semiconductor pattern.