US 11,387,229 B2Granted

Semiconductor device

AssigneeSamsung Electronics Co., Ltd.

InventorsJaeha Lee, Ha-Young Kim, Bonghyun Lee, Soyoung Lee, Yongeun Cho

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Abstract

Disclosed is a semiconductor device comprising a logic cell including first and second active regions spaced apart in a first direction on a substrate, first and second active patterns on the first and second active regions and extend in a second direction, first and second source/drain patterns on the first and second active patterns, gate electrodes extending in the first direction to run across the first and second active patterns and arranged in the second direction at a first pitch, first lines in a first interlayer dielectric layer on the gate electrodes and each electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and second lines in a second interlayer dielectric layer on the first interlayer dielectric layer and extending parallel to each other in the first direction.

Claims20

Dependent claims

A semiconductor device, comprising:

a logic cell on a substrate, the logic cell including a first active region and a second active region spaced apart in a first direction;
a first active pattern on the first active region, and a second active pattern on the second active region, the first and second active patterns extending in a second direction that intersects the first direction;
a first source/drain pattern on an upper portion of the first active pattern and a second source/drain pattern on an upper portion of the second active pattern;
a plurality of gate electrodes that run across the first and second active patterns and extend in the first direction, the gate electrodes arranged in the second direction at a first pitch;
a plurality of first lines in a first interlayer dielectric layer on the gate electrodes, each of the first lines being electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and the first lines extending parallel to each other in the second direction;
and
a plurality of second lines in a second interlayer dielectric layer on the first interlayer dielectric layer, the second lines extending parallel to each other in the first direction,
wherein
the first lines include first to third pin lines,
the second lines include first to third routing lines,
the first to third pin lines are electrically connected respectively to the first to third routing lines,
a length in the second direction of each of the first to third pin lines is less than twice the first pitch,
a first overlap region is defined where adjacent ones of the first to third pin lines overlap each other in the first direction, and
a length in the second direction of the first overlap region is less than the first pitch.

11 more elements

A semiconductor device, comprising:

a logic cell on a substrate, the logic cell including a first active region and a second active region spaced apart in a first direction;
a first active pattern on the first active region and a second active pattern on the second active region, the first and second active patterns extending in a second direction that intersects the first direction;
a device isolation layer that covers lower sidewalls of the first and second active patterns, an upper portion of each of the first and second active patterns vertically protruding upwards from the device isolation layer;
a first source/drain pattern on the upper portion of the first active pattern and a second source/drain pattern on the upper portion of the second active pattern;
a plurality of gate electrodes that run across the first and second active patterns and extend in the first direction, the gate electrodes arranged in the second direction at a first pitch;
a plurality of first lines in a first interlayer dielectric layer on the gate electrodes, each of the first lines being electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and the first lines extending parallel to each other in the second direction;
and
a plurality of second lines in a second interlayer dielectric layer on the first interlayer dielectric layer, the second lines extending parallel to each other in the first direction,
wherein
the first lines include first to third pin lines,
the second lines include first to third routing lines,
the first to third pin lines are electrically connected respectively to the first to third routing lines,
a length in the second direction of each of the first to third pin lines is less than twice the first pitch,
a first overlap region is defined where the first to third pin lines overlap each other in the first direction, and
a length in the second direction of the first overlap region is less than the first pitch.

12 more elements

A semiconductor device, comprising:

a logic cell on a substrate, the logic cell including a first active region and a second active region spaced apart in a first direction;
a first active pattern on the first active region and a second active pattern on the second active region, the first and second active patterns extending in a second direction that intersects the first direction, the first active pattern including a plurality of first channel patterns that are vertically stacked, and the second active pattern including a plurality of second channel patterns that are vertically stacked;
a first source/drain pattern and a second source/drain pattern, the first source/drain pattern being on one side of the first channel patterns, and the second source/drain pattern being on one side of the second channel patterns;
a plurality of gate electrodes that run across the first and second active patterns and extend in the first direction, the gate electrodes arranged in the second direction at a first pitch;
a plurality of first lines in a first interlayer dielectric layer on the gate electrodes, each of the first lines being electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and the first lines extending parallel to each other in the second direction;
and
a plurality of second lines in a second interlayer dielectric layer on the first interlayer dielectric layer, the second lines extending parallel to each other in the first direction,
wherein
a first gate electrode of the gate electrodes is on a top surface, a bottom surface, and opposite sidewalls of each of the first channel patterns,
a second gate electrode of the gate electrodes is on a top surface, a bottom surface, and opposite sidewalls of each of the second channel patterns,
the first lines include first to third pin lines,
the second lines include first to third routing lines,
the first to third pin lines are electrically connected respectively to the first to third routing lines,
a length in the second direction of each of the first to third pin lines is less than twice the first pitch,
a first overlap region is defined where the first to third pin lines overlap each other in the first direction, and
a length in the second direction of the first overlap region is less than the first pitch.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/826,756Filed 23 Mar 2020
Priority: KR 10-2019-007101914 Jun 2019
Published: US 2020/0395354 A117 Dec 2020
Granted: 12 Jul 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F 30/394
Circuit design at the physical level: routing
G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…