Memory device having multiple chips and method for manufacturing the same
AssigneeKioxia Corporation
InventorMutsumi Okajima
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a memory device includes: a first chip including a first insulating layer and a first pad; a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals in a first direction parallel to a surface of the first chip; a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals in the first direction; a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and a circuit provided in the second chip.
Claims15
A memory device comprising:
- a first chip including a first insulating layer and a first pad;
- a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals along a first direction parallel to a surface of the first chip, each of the plurality of memory units including a first columnar portion extending along a second direction in the first insulating layer, the second direction being perpendicular to the surface of the first chip;
- a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals along the first direction, each of the plurality of mark portions including a second columnar portion extending along the second direction in the first insulating layer;
- a second chip including a second pad connected to the first pad and overlapping the first chip along the second direction;
- and
- a circuit provided in the second chip,
- wherein
- the plurality of mark portions are electrically isolated from the plurality of memory units and the circuit,
- the first columnar portion includes a capacitor,
- the capacitor includes a first conductive portion, a second conductive portion, and a first insulating portion between the first conductive portion and the second conductive portion,
- the second columnar portion includes a third conductive portion, a fourth conductive portion, and a second insulating portion between the third conductive portion and the fourth conductive portion,
- a material of the first conductive portion is identical to a material of the third conductive portion,
- a material of the second conductive portion is identical to a material of the fourth conductive portion, and
- a material of the first insulating portion is identical to a material of the second insulating portion.
A memory device comprising:
- a first chip including a first insulating layer and a first pad;
- a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals along a first direction parallel to a surface of the first chip;
- a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals along the first direction;
- a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip;
- and
- a circuit provided in the second chip,
- wherein each of the plurality of memory units includes a first magnetic body and a reading element connected to one end of the magnetic body.
Dependencies are inferred from the claim text.