Integrated circuit package and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Chieh-Yen Chen
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Abstract
In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.
Claims20
A structure comprising:
- a processor device comprising a semiconductor substrate, the semiconductor substrate comprising active devices interconnected to form logic devices;
- a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds;
- a first dielectric layer laterally surrounding the first memory device;
- a redistribution structure over the first dielectric layer and the first memory device, sidewalls of the redistribution structure being laterally coterminous with sidewalls of the semiconductor substrate and with sidewalls of the first dielectric layer, the redistribution structure comprising metallization patterns;
- and
- first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.
A structure comprising:
- a processor device having a front side, the processor device comprising a semiconductor substrate and an interconnect structure, the interconnect structure disposed at the front side of the processor device;
- a first memory device having a front side and a back side opposite the front side, the front side of the first memory device connected to the front side of the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds;
- a first dielectric layer laterally surrounding the first memory device, sidewalls of the first dielectric layer being laterally coterminous with sidewalls of the semiconductor substrate and with sidewalls of the interconnect structure;
- first conductive vias extending through the first dielectric layer, the first conductive vias connected to the front side of the processor device;
- a second memory device having a front side and a back side opposite the front side, the front side of the second memory device connected to the first conductive vias and the back side of the first memory device by metal-to-metal bonds, the front side of the second memory device connected to the first dielectric layer and the back side of the first memory device by dielectric-to-dielectric bonds, the first memory device being a different type of memory device than the second memory device;
- and
- a second dielectric layer laterally surrounding the second memory device.
A method comprising:
- bonding a first memory device to a wafer, the wafer comprising a processor device, the processor device comprising a semiconductor substrate and die connectors, the first memory device comprising first conductive vias;
- forming a first dielectric layer around the first memory device;
- patterning first openings in the first dielectric layer, the first openings exposing the die connectors of the processor device;
- plating a conductive material in the first openings and on the die connectors;
- planarizing the conductive material to form second conductive vias in the first openings, the planarizing exposing the first conductive vias of the first memory device;
- and
- sawing the first dielectric layer and the wafer to singulate the processor device, sidewalls of the first dielectric layer being laterally coterminous with sidewalls of the semiconductor substrate of the processor device.
Dependencies are inferred from the claim text.