Semiconductor device and method of manufacture
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
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Abstract
An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.
Claims20
A method of manufacturing a semiconductor device, the method comprising:
- encapsulating a semiconductor die, a first set of through vias, and a reference via with an encapsulant;
- exposing the first set of through vias and the reference via with a planarization process on a first side of the semiconductor die;
- connecting the first set of through vias on a second side of the semiconductor die opposite the first side to a second semiconductor die;
- performing a single singulation process to expose a sidewall of the reference via;
- and
- depositing a lid in physical contact with the sidewall of the reference via.
A method of manufacturing a semiconductor device, the method comprising:
- encapsulating a semiconductor die, a first set of through vias, and a reference via with an encapsulant;
- planarizing a first side of the encapsulant to expose the first set of through vias and the reference via;
- connecting a second side of the first set of through vias opposite the first side to a second semiconductor die;
- exposing a top surface of the reference via with a first singulation process;
- exposing a sidewall of the reference via with a second singulation process different from the first singulation process;
- and
- depositing a lid in physical contact with both the top surface of the reference via and the sidewall of the reference via.
A method of manufacturing a semiconductor device, the method comprising:
- planarizing a reference via, a first die, a through via, and an encapsulant together;
- reducing a thickness of the reference via with a first singulation process;
- exposing a sidewall of the reference via with a second singulation process different from the first singulation process;
- and
- forming a lid in physical contact with the sidewall of the reference via, wherein after the forming the lid the lid covers a first package electrically connected with the through via.
Dependencies are inferred from the claim text.