Semiconductor memory device
AssigneeSK hynix Inc.
InventorsJin Ho Kim, Young Ki Kim, Sang Hyun Sung, Sung Lae Oh, Byung Hyun Jun
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Abstract
A semiconductor memory device includes a plurality of first pads disposed in one surface of a memory chip which includes a memory cell array and a plurality of row lines coupled to the memory cell array, and coupled to the row lines, respectively; and a plurality of second pads disposed in one surface of a circuit chip which is boned to the one surface of the memory chip, coupled to pass transistors, respectively, of the circuit chip, and bonded to the first pads, respectively. The second pads are aligned with the pass transistors, with the same pitch as a pitch of the pass transistors.
Claims17
A semiconductor memory device comprising:
- a plurality of first pads, disposed in one surface of a memory chip,
- a plurality of row lines, included in a memory cell array of the memory chip;
- and
- a plurality of second pads, disposed in one surface of a circuit chip and bonded to the plurality of first pads, coupled to a plurality of pass transistors of the circuit chip,
- wherein each of the plurality of row lines terminates in a step portion that projects further than above row lines,
- wherein the plurality of first pads is coupled to the plurality of row lines through the step portions,
- wherein the second pads are aligned with the pass transistors at the same pitch as a pitch of the pass transistors.
A semiconductor memory device comprising:
- a plurality of first pads, disposed in one surface of a memory chip, coupled to a plurality of row lines, included in a memory cell array of the memory chip;
- a plurality of second pads, disposed in one surface of a circuit chip and bonded to the plurality of first pads, coupled to a plurality of pass transistors of the circuit chip;
- and
- a shield pattern disposed in the pad-free zone, and having a constant potential independent of an operation of the memory chip or the circuit chip,
- wherein the second pads are aligned with the pass transistors at the same pitch as a pitch of the pass transistors,
- wherein the first pads are disposed in a first pad layer of the one surface of the memory chip, and the second pads are disposed in a second pad layer of the one surface of the circuit chip, and
- wherein each of the first and second pad layers includes a pad-free zone where the first and second pads are not disposed, and the pad-free zone does not overlap with the pass transistors.
A semiconductor memory device comprising:
- a memory chip, and a circuit chip bonded onto the memory chip,
- wherein the memory chip includes a memory cell array having a plurality of row lines, and a first pad layer with a plurality of first pads,
- wherein each of the plurality of row lines terminates in a step portion that projects further than above row lines,
- wherein the plurality of first pads is coupled to the plurality of row lines through the step portions,
- wherein the circuit chip includes a plurality of pass transistors, and a second pad layer with a plurality of second pads that are respectively coupled to the plurality of pass transistors and respectively bonded to the plurality of first pads and
- wherein each of the plurality of second pads is disposed within a pitch of a corresponding pass transistor.
Dependencies are inferred from the claim text.