US 11,387,214 B2 · Multi-chip modules formed using wafer-level processing of a reconstituted wafer

Abstract

Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.

Claims20

Dependent claims

A method, comprising:

providing a first die in a reconstituted form in which the first die is at least partially surrounded by a first molding layer, a pad layer disposed over the first die and including at least one contact;
providing at least one second die at least partially surrounded by a second molding layer and directly bonded to the first die by way of a direct bonded interconnect, the at least one second die including at least one contact directly bonded and in contact with the at least one contact of the pad layer without an intervening solder ball;
and
forming at least one conductor through the first molding layer, the least one conductor being in contact with the second die.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

16/712,357Filed 12 Dec 2019 · continuation

Priority

15 Jun 2017

Published

US 2020/0118973 A116 Apr 2020

Granted

12 Jul 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification35 codes

H10W 90/00
Package configurations
H10W 20/056
Of conductive parts of the interconnections: by filling conductive material into holes, grooves or trenches
H10W 70/09
By depositing layers on the chip or wafer, e.g. "chip-first" RDLs: extending onto an encapsulation that laterally surrounds the chip or wafer,…
H10W 70/60
Package substrates; Interposers; Redistribution layers [RDL]: insulating or insulated package substrates; Interposers; Redistribution layers

Family

Application15/624,494Parent of this division · filed 15 Jun 2017

Application16/246,863Parent of this continuation · filed 14 Jan 2019

US 10,217,720 B2Parent of this division · filed 26 Feb 2019

US 2020/0118973 A1Pre-grant publication · published 16 Apr 2020

US 10,546,834 B2Parent of this continuation

Application16/246,863Parent of this division

US 2018/0366436 A1Published application

US 2019/0148339 A1Published application

US 11,387,214 B2This patent

From the US filing history. Foreign family members aren’t listed.

Multi-chip modules formed using wafer-level processing of a reconstituted wafer

Life of this patent

Multi-chip modules formed using wafer-level processing of a reconstituted wafer

Life of this patent

Abstract

Claims20