Method for manufacturing a semiconductor package
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorShun Sing Liao
Life of this patent
Estimating the term…
Abstract
A method for manufacturing a semiconductor package includes: (a) providing a substrate structure, wherein the substrate structure includes a chip attach area, a bottom area opposite to the chip attach area, a lower side rail surrounding the bottom area, a first lower structure and a second lower structure, wherein the first lower structure is disposed in a first lower region of the lower side rail, and a second lower occupancy ratio is greater than a first lower occupancy ratio; (b) attaching at least one semiconductor chip to the chip attach area; and (c) forming an encapsulant to cover the at least one semiconductor chip.
Claims20
A method for manufacturing a semiconductor package, comprising:
- (a) providing a substrate structure, wherein the substrate structure includes a chip attach area, an upper side rail surrounding the chip attach area, a first upper structure, a second upper structure, a bottom area opposite to the chip attach area, a lower side rail surrounding the bottom area, a first lower structure and a second lower structure, wherein the first upper structure is disposed in a first upper region of the upper side rail, the second upper structure is disposed in a second upper region surrounding the first upper region, the first lower structure is disposed in a first lower region of the lower side rail, the second lower structure is disposed in a second lower region surrounding the first lower region, wherein a stress relieving ability of the first lower structure is less than a stress relieving ability of the first upper structure, and a structural strength of the second lower structure is greater than a structural strength of the second upper structure;
- (b) attaching at least one semiconductor chip to the chip attach area;
- and
- (c) forming an encapsulant to cover the at least one semiconductor chip.
A substrate structure comprising:
- a first lower structure disposed in a first lower region surrounding a bottom area opposite to a chip attach area, wherein a first lower occupancy ratio is defined as a ratio of an area of the first lower structure from a bottom view to an area of the entire first lower region from a bottom view;
- and
- a second lower structure disposed in a second lower region surrounding the first lower region, wherein a second lower occupancy ratio is defined as a ratio of an area of the second lower structure from a bottom view to an area of the entire second lower region from a bottom view, and the second lower occupancy ratio is greater than the first lower occupancy ratio,
- wherein a stress relieving ability of the first lower structure is greater than a stress relieving ability of the second lower structure, and a structural strength of the second lower structure is greater than a structural strength of the first lower structure.
A substrate structure comprising:
- a first lower structure disposed in a first lower region surrounding a bottom area opposite to a chip attach area;
- and
- a second lower structure disposed in a second lower region surrounding the first lower region, wherein a width of the second lower region is greater than a width of the first lower region, a second lower occupancy ratio is defined as a ratio of an area of the second lower structure from a bottom view to an area of the entire second lower region from a bottom view, and the second lower occupancy ratio is greater than 80%
- wherein a stress relieving ability of the first lower structure is greater than a stress relieving ability of the second lower structure, and a structural strength of the second lower structure is greater than a structural strength of the first lower structure.
Dependencies are inferred from the claim text.