Three-dimensional semiconductor device including a through-via structure having a via liner having protruding portions

A three-dimensional semiconductor device comprising:

• a word line stack above a substrate having a cell area and an extension area, the word line stack including mold layers and word lines alternately stacked, the word line stack horizontally extending in the cell area and having a staircase structure in the extension area;
• and
• vertical channel structures, a word line cut structure, and a first through-via structure vertically penetrating the word line stack, the first through-via structure including a first via plug and a first via liner layer surrounding sidewalls of the first via plug, and first dents being on an inner sidewall of the first via liner layer, each first dent is between a top surface and a bottom surface of a corresponding word line;
• wherein the word line stack includes a lower word line stack and an upper word line stack,
• the mold layers include lower mold layers and upper mold layers,
• the word lines include lower word lines and upper word lines,
• the lower word line stack includes the lower mold layers and the lower word lines alternately stacked,
• the upper word line stack includes the upper mold layers and the upper word lines alternately stacked,
• the lower word line stack and the upper word line stack horizontally extend in the cell area, and
• the lower word line stack and the upper word line stack include staircase structures having a flat zone shaped in a staircase landing in the extension area, and
• the first through-via structure is in the flat zone.

A three-dimensional semiconductor device comprising:

• a substrate having a cell area, a dummy area, and an extension area;
• a logic device layer on the substrate and including a transistor and a via pad;
• a lower interlayer insulating layer on the logic device layer;
• a common source layer in the lower interlayer insulating layer;
• a lower word line stack and a lower staircase insulating layer on the lower insulating layer;
• an upper word line stack on the lower word line stack;
• an upper staircase insulating layer on the lower staircase insulating layer;
• vertical channel structures and a word line cut structure vertically penetrating the lower word line stack and the upper word line stack to be connected with the common source layer in the cell area;
• a dummy vertical channel structure vertically penetrating the lower word line stack and the upper word line stack to be connected with the common source layer in the dummy area;
• and
• a first through-via structure vertically penetrating a portion of the lower word line stack to be electrically connected the via pad in the extension area, the first through-via structure including a first via plug and a first via liner layer surrounding sidewalls of the first via plug, inner sidewalls of the first via liner layer including seams at the same levels as the word lines of the word line stack, and the seams having a ring shape or a disk shape in a plan view, each seam is between a top surface and a bottom surface of a corresponding word line.