Module structure and method for manufacturing the module structure

A method for manufacturing a module structure, comprising:

• providing a substrate;
• disposing at least one passive element on the substrate;
• and
• disposing at least two metal columns and at least one chip on a side of the at least one passive element away from the substrate;
• wherein a vertical projection of the at least one chip on the substrate overlaps a line segment or closed figure formed by connecting endpoints constituted by vertical projections of the at least two metal columns on the substrate;
• wherein at least one of the following applies:
• a vertical projection of the at least one passive element on the substrate overlaps the line segment or closed figure formed by connecting the endpoints constituted by the vertical projections of the at least two metal columns on the substrate;
• or a vertical projection of the at least one passive element on the substrate overlaps the vertical projection of the at least one chip on the substrate;
• wherein disposing the at least two metal columns and the at least one chip on the side of the at least one passive element away from the substrate comprises:
• forming a first dielectric layer on a side of the substrate adjacent to the at least one passive element, wherein the first dielectric layer covers or wraps the at least one passive element, a first via is formed in the first dielectric layer, and a first conductor is formed in the first via;
• forming a first connection layer on a side of the first dielectric layer away from the substrate;
• and
• disposing the at least two metal columns and the at least one chip on a side of the first dielectric layer away from the at least one passive element, wherein the at least one passive element is electrically connected to at least one of the at least two metal columns or the at least one chip through the first conductor and the first connection layer;
• and
• wherein the method further comprises:
• forming a second dielectric layer on a side of the first dielectric layer away from the substrate;
• forming a second connection layer on a side of the second dielectric layer away from the substrate, wherein a second via is formed in the second dielectric layer, a second conductor is formed in the second via, and the at least two metal columns are electrically connected to the at least one chip through the second conductor and the second connection layer;
• and
• forming a third dielectric layer on a side of the second dielectric layer away from the substrate, wherein the third dielectric layer covers the second dielectric layer.