IC package with half-bridge power module

An integrated circuit (IC) package comprising:

• a substrate comprising a first region and a second region, wherein the substrate includes a conductive path between the first region and the second region;
• a lead frame comprising a first member and a second member that are spaced apart;
• and
• a half-bridge power module comprising:
• a capacitor having a first node coupled to the first member of the lead frame and a second node coupled to the second member of the lead frame, wherein the capacitor is mounted in a plane parallel to a planer surface of the substrate;
• a high side die comprising a plurality of high side field effect transistors (FET) embedded therein;
• and
• a low side die comprising a plurality of low side FETs embedded therein, wherein a source of each high side FET in the plurality of high side FETs is coupled to a drain of a respective low side FET of the plurality of low side FETs through the conductive path between the first region and the second region of the substrate and a drain of each high side FET in the plurality of high side FETs and a source of each low side FET in the plurality of low side FETs are coupled to the capacitor.

A method for forming an integrated circuit (IC) package, the method comprising:

• adhering a high side die and a low side die to a substrate, wherein the high side die comprises a plurality of high side field effect transistors (FETs) and the low side die comprises a plurality of low side FETs;
• adhering a lead frame to the substrate, the lead frame having a first member and a second member that are spaced apart;
• adhering a capacitor to the lead frame, such that the capacitor extends in a plane that is parallel from a planer surface of the substrate;
• and
• applying wire bonding to couple a source of each high side FET in the plurality of high side FETs to a drain of a respective low side FET of the plurality of low side FETs and to couple a drain of each high side FET in the plurality of high side FETs and a source of each low side FET in the plurality of low side FETs to the capacitor.