A semiconductor structure, comprising:
- field effect transistors located on a substrate;
- a three-dimensional memory array located over the substrate, wherein the three-dimensional memory array comprises at least one alternating stack of insulating layers and electrically conductive layers and memory stack structures comprising a vertical semiconductor channel and a memory film that vertically extend through the at least one alternating stack, and wherein the at least one alternating stack comprises stepped surfaces in a staircase region;
- at least one retro-stepped dielectric material portion overlying the stepped surfaces and the field effect transistors;
- and
- a contact via structure extending from a first horizontal plane including a topmost surface of the at least one retro-stepped dielectric material portion to a component of the field effect transistors,
- wherein the contact via structure has:
- a first portion having a first width at a first height from a second horizontal plane including the top surface of the substrate;
- a second portion having a second width that is greater than the first width at a second height from the second horizontal plane that is less than the first height;
- a third portion having a third width that is greater than the first width at a third height from the second horizontal plane that is less than the second height;
- and
- a fourth portion having a fourth width that is less than the second width and is less than the third width at a fourth height at which a bottommost surface of the contact via structure is located,
- wherein the at least one alternating stack comprises a first-tier alternating stack of first insulating layers and first electrically conductive layers, and a second-tier alternating stack of second insulating layers and second electrically conductive layers, wherein the second-tier alternating stack is located over the first-tier alternating stack,
- wherein the at least one retro-stepped dielectric material portion comprises a first retro-stepped dielectric material portion contacting, and overlying, stepped surfaces of the first-tier alternating stack, and a second retro-stepped dielectric material portion contacting, and overlying, stepped surfaces of the second-tier alternating stack, and
- wherein the second retro-stepped dielectric material portion comprises:
- a doped silicate glass liner including a sloping portion that contacts the stepped surfaces of the second-tier alternating stack;
- and
- a silicate glass material portion overlying the doped silicate glass liner and including a planar top surface and a tapered portion overlying, and vertically spaced from, the stepped surfaces of the second-tier alternating stack.