Multi-layer cooling structure including through-silicon vias through a plurality of directly-bonded substrates and methods of making the same
AssigneeToyota Motor Engineering & Manufacturing North America, Inc.
InventorsFeng Zhou, Ki Wook Jung, Ercan M. Dede
Life of this patent
Estimating the term…
Abstract
A multi-layer cooling structure comprising a first substrate layer comprising an array of cooling channels, a second substrate layer comprising a nozzle structure that includes one or more nozzles, an outlet, and an outlet manifold, a third substrate layer comprising an inlet manifold and an inlet, and one or more TSVs disposed through the first substrate layer, second substrate layer, and third substrate layer. At least one of the one or more TSVs is metallized. The first substrate layer and the second substrate layer are directly bonded, and the second substrate layer and the third substrate layer are directly bonded.
Claims20
A method of fabricating a multi-layer cooling structure comprising one or more TSVs through a first substrate layer that comprises an array of cooling channels, a second substrate layer that comprises a nozzle structure, and a third substrate layer for thermally coupling to and cooling a semiconductor device, the method comprising:
- patterning three silicon wafers to form the first substrate layer, the second substrate layer, and the third substrate layer, such that one or more through-holes extend through the first substrate layer, the second substrate layer, and the third substrate layer;
- directly bonding the first substrate layer to the second substrate layer and the second substrate layer to the third substrate layer to form a multi-layer substrate;
- and
- depositing a metallization layer in the one or more through-holes to form a TSV.
A method of fabricating a multi-layer cooling structure comprising one or more TSVs through a first substrate layer that comprises an array of cooling channels, a second substrate layer that comprises a nozzle structure, and a third substrate layer for thermally coupling to and cooling a semiconductor device, the method comprising:
- etching a cooling fluid inlet and a cooling fluid outlet on the third substrate layer;
- etching one or more through-holes through the first substrate layer, the second substrate layer, and the third substrate layer;
- aligning the one or more through-holes of the first substrate layer, the second substrate layer, and the third substrate layer;
- directly bonding the first substrate layer to the second substrate layer and the second substrate layer to the third substrate layer;
- and
- depositing a metallization layer in the one or more through-holes to form a TSV.
Dependencies are inferred from the claim text.