Chip package

A chip package, comprising:

• a chip;
• a chip carrier carrying the chip and electrically connected to the chip;
• a heat dissipation stack structure located at a side of the chip carrier opposite to a side carrying the chip, the heat dissipation stack structure comprising:
• a first thermal interface material layer;
• a second thermal interface material layer stacked on the first thermal interface material layer;
• a third thermal interface material layer stacked on the second thermal interface material layer and located between the chip carrier and the second thermal interface material layer, wherein a material of the second thermal interface material layer is different from a material of the first thermal interface material layer and a material of the third thermal interface material layer, the second thermal interface material layer completely separates the first thermal interface material layer from the third thermal interface material layer;
• and
• a heat-dissipating device overlapped with the first thermal interface material layer, wherein the first thermal interface material layer is interposed between the heat-dissipating device and the second thermal interface material layer, and the heat dissipation stack structure comprises a coterminous outer sidewall provided by a sidewall of the heat-dissipating device, a sidewall of the first thermal interface material layer, a sidewall of the second thermal interface material layer, and a sidewall of the third thermal interface material layer;
• and
• an insulating encapsulant encapsulating the chip, the heat dissipation stack structure, and the chip carrier and exposing a portion of the chip carrier.