Memory device, memory system including the same and methods of operation

A memory system comprising:

• a memory device;
• and
• a memory controller,
• the memory device comprising:
• a first wafer including a first bonding pad disposed on a first surface;
• a second wafer stacked on the first surface of the first wafer in a vertical direction that is perpendicular to the first surface of the first wafer, including a second bonding pad disposed on a second surface of the second wafer corresponding to the first bonding pad, bonded on the first wafer such that the second bonding pad is aligned to the first bonding pad;
• and
• a first test pattern,
• the first test pattern comprising:
• a pair of first test pads disposed on the first surface and electrically coupled to each other;
• a pair of second test pads disposed on the second surface of the second wafer and respectively coupled to the pair of first test pads;
• and
• a pair of third test pads disposed on a third surface of the second wafer, which is opposite to the second surface in the vertical direction, and respectively coupled to the pair of second test pads,
• wherein the memory controller applies a test voltage to one of the pair of third test pads and generates a power-up signal based on a ratio between a detection voltage measured from the other third test pad and the test voltage, and
• wherein the first wafer provides a boosted voltage to the first bonding pad in response to the power-up signal.

A method of detecting a pad misalignment in a memory device comprising:

• providing
• a first wafer including a first bonding pad disposed on a first surface;
• a second wafer stacked on the first surface of the first wafer in a vertical direction that is perpendicular to the first surface of the first wafer, including a second bonding pad disposed on a second surface of the second wafer and corresponding to the first bonding pad, the second surface of the second wafer bonded on the first surface of the first wafer;
• and
• a first test pattern,
• the first test pattern comprising:
• a pair of first test pads disposed on the first surface and electrically coupled to each other;
• a pair of second test pads disposed on the second surface of the second wafer and respectively coupled to the pair of first test pads;
• and
• a pair of third test pads disposed on a third surface of the second wafer, which is opposite to the second surface in the vertical direction, and respectively coupled to the pair of second test pads;
• applying a test signal to one of the pair of third test pads;
• measuring an output signal from the other of the pair of third test pads;
• and
• detecting a pad misalignment based on the output signal.