Fabricating method of decreasing height difference of STI

A method of decreasing height differences of shallow trench isolations (STIs), comprising:

• providing a substrate comprising a core circuit region and a peripheral circuit region, wherein the peripheral circuit region comprises a P-type transistor region and an N-type transistor region, and wherein a pad oxide covers the substrate;
• forming a first STI, a second STI and a third STI respectively disposed within the N-type transistor region of the peripheral circuit region, the core circuit region and the P-type transistor region of the peripheral circuit region, wherein the first STI, the second STI and the third STI are embedded within the pad oxide and the substrate, a top surface of the first STI protrudes a height from a top surface of the substrate, a top surface of the second STI protrudes the height from the top surface of the substrate, a top surface of the third STI protrudes the height from the top surface of the substrate;
• forming a first mask to cover the core circuit region and the N-type transistor region and to expose the third STI and the P-type transistor region of the peripheral circuit region;
• forming an N-type well by doping N-type dopants into the P-type transistor region which is exposed through the first mask and removing part of the third STI which is exposed through the first mask to make the top surface of the third STI protrude a first distance from the top surface of the substrate, and the first distance is smaller than the height;
• removing the first mask;
• forming a second mask to cover the core circuit region and the P-type transistor region and to expose the first STI and the N-type transistor region of the peripheral circuit region;
• forming a P-type well by doping P-type dopants into the N-type transistor region which is exposed through the second mask and removing part of the first STI which is exposed through the second mask to make the top surface of the first STI protrude a second distance from the top surface of the substrate, and the second distance is smaller than the height;
• removing the second mask;
• after forming the P-type well and the N-type well, forming a first silicon oxide layer to replace the pad oxide;
• after forming the first silicon oxide layer, forming a third mask to cover the peripheral circuit region and to expose the second STI and the first silicon oxide layer within the core circuit region;
• removing part of the second STI and an entirety of the first silicon oxide layer within the core circuit region by taking the third mask as a mask so as to make the top surface of the second STI protrude a third distance from the top surface of the substrate, wherein the third distance is smaller than the height;
• and
• removing the third mask.