Multifunction single via patterning
AssigneeInternational Business Machines Corporation
InventorEffendi Leobandung
Life of this patent
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Abstract
A method for semiconductor device fabrication includes forming storage elements on conductive structures. An interlevel dielectric (ILD) layer is formed over the storage elements. Trenches are patterned in the ILD layer to expose a top portion of the storage elements. The storage elements where interlevel vias are to be formed is removed. A conductive material is deposited in the trenches and the via openings to concurrently make contact with the storage elements and form interlevel vias in the via openings.
Claims20
A method for semiconductor device fabrication, comprising:
- forming storage elements on conductive structures;
- forming an interlevel dielectric (ILD) layer over the storage elements;
- patterning trenches in the ILD layer;
- removing the storage elements where interlevel vias are to be formed to expose the conductive structures therebelow to form via openings;
- and
- depositing a conductive material in the trenches and the via openings.
A method for semiconductor device fabrication, comprising:
- forming a stack of layers over an underlying layer having conductive structures formed therein, the stack of layers including at least an electrode layer and a memory material layer;
- patterning the stack of layers to form storage elements on conductive structures;
- forming an interlevel dielectric (ILD) layer over the storage elements;
- patterning trenches in the ILD layer;
- removing the storage elements where interlevel vias are to be formed to expose the conductive structures therebelow to form via openings;
- and
- depositing a conductive material in the trenches and the via openings.
Dependencies are inferred from the claim text.