Enlarging contact area and process window for a contact via

An integrated chip comprising:

• a substrate comprising a source/drain region;
• a contact layer arranged over the source/drain region;
• a gate electrode arranged over the substrate and laterally spaced from the contact layer;
• a hard mask structure arranged over the gate electrode;
• a contact via extending through the hard mask structure and arranged over and directly contacting an upper surface of the gate electrode;
• a spacer structure arranged directly between the gate electrode and the contact layer;
• and
• a liner layer contacting inner sidewalls of the spacer structure, wherein the liner layer comprises a material with a higher dielectric constant than a material of the spacer structure.

An integrated chip comprising:

• a substrate;
• a gate electrode overlying the substrate;
• a contact layer overlying the substrate and laterally spaced from the gate electrode;
• a spacer structure surrounding outermost sidewalls of the gate electrode and separating the gate electrode from the contact layer;
• a hard mask structure arranged over the gate electrode and between portions of the spacer structure;
• and
• a liner layer arranged directly between the hard mask structure and the spacer structure, wherein a bottommost surface of the hard mask structure is arranged below a bottommost surface of the liner layer.