Integrated circuit isolation feature and method of forming the same

A method comprising:

• receiving a workpiece having:
• a plurality of semiconductor fins, and
• a recess defined between two adjacent ones of the plurality of semiconductor fins;
• depositing a first flowable dielectric within the recess that includes a semiconductor component and oxygen;
• depositing a second flowable dielectric on the first flowable dielectric within the recess, wherein the second flowable dielectric includes the semiconductor component and is free of oxygen;
• performing an annealing process on the workpiece such that oxygen migrates from the first flowable dielectric to the second flowable dielectric so as to form a third dielectric layer;
• and
• after the performing of the anneal process, planarizing the workpiece until a top surface of the third dielectric layer and top surfaces of the plurality of semiconductor fins are coplanar.

A method comprising:

• receiving a workpiece that includes:
• a plurality of fins,
• a recess defined between two adjacent ones of the plurality of fins, the recess having a bottom surface;
• depositing a first dielectric precursor on the bottom surface of the recess using flowable chemical vapor deposition (FCVD), the first dielectric precursor comprising oxygen;
• etching back the deposited first dielectric precursor;
• after the etching back, depositing a second dielectric precursor within the recess and on the first dielectric precursor, the second dielectric precursor being free of oxygen;
• annealing the workpiece at an anneal temperature greater than 600° C. to diffuse oxygen from the first dielectric precursor to the second dielectric precursor so as to form a third dielectric layer;
• and
• after the annealing, planarizing the workpiece until a top surface of the third dielectric layer and top surfaces of the plurality of fins are coplanar.