Component carrier with included electrically conductive base structure and method of manufacturing

A method for manufacturing a component carrier, the method comprising:

• forming a base structure consisting of an electrically conductive material;
• forming a surrounding structure on the base structure, the surrounding structure being electrically insulating and defining a cavity;
• forming an electrically conductive layer that at least partially covers the surrounding structure and at least partially covers the base structure;
• introducing an electronic component in the cavity such that a part of the electrically conductive layer is arranged between the electronic component and the base structure,
• wherein the electronic component is selected from a group consisting of an electrically non-conductive inlay, an electrically conductive inlay, a heat transfer unit, a die, an active electronic component, a passive electronic component, a filter, an integrated circuit, a signal processing component, a power management component, a voltage converter, a cryptographic component, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductance, a battery, a switch, a camera, a logic chip, an energy harvesting unit, a magnetic element, a substrate, an interposer, a further component carrier;
• applying a further electrically insulating layer structure on top of the surrounding structure,
• wherein the further electrically insulating layer structure is not optically transparent and at least partially fills a gap between the electronic component and the surrounding structure such that the electronic component is at least partially embedded in the component carrier;
• wherein the component carrier further comprises a plurality of vias formed at least partially through the further electrically insulating layer structure,
• wherein the plurality of vias form a redistribution structure, and
• wherein at least a part of the plurality of vias is arranged directly on a main surface of the embedded electronic component.

A method of using a copper layer, the method comprising:

• providing a base structure consisting of an electrically conductive material;
• fabricating a surrounding structure of an electrically insulating material on the base structure, the surrounding structure defining a cavity;
• fabricating the copper layer by electroplating such that the copper layer at least partially covers the surrounding structure and at least partially covers the base structure;
• and
• arranging an electronic component in the cavity on the copper layer, wherein the surrounding structure at least partially surrounds the electronic component,
• wherein the electronic component is selected from a group consisting of an electrically non-conductive inlay, an electrically conductive inlay, a heat transfer unit, a die, an active electronic component, a passive electronic component, a filter, an integrated circuit, a signal processing component, a power management component, a voltage converter, a cryptographic component, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductance, a battery, a switch, a camera, a logic chip, an energy harvesting unit, a magnetic element, a substrate, an interposer, a further component carrier;
• wherein the copper layer directly contacting the electronic component and arranged between the electronic component and the base structure in a component carrier is a heat dissipation and stiffening structure for said component carrier;
• applying a further electrically insulating layer structure on top of the surrounding structure,
• wherein the further electrically insulating layer structure is not optically transparent at least partially fills a gap between the electronic component and the surrounding structure such that the electronic component is at least partially embedded in the component carrier;
• wherein the component carrier further comprises a plurality of vias formed at least partially through the further electrically insulating layer structure,
• wherein the plurality of vias form a redistribution structure, and
• wherein at least a part of the plurality of vias is arranged directly on a main surface of the embedded electronic component.