Loading effect reduction through multiple coat-etch processes
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
Life of this patent
Estimating the term…
Loading patent…
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
Estimating the term…
First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
A method of fabricating a semiconductor device, comprising:
A method of fabricating a semiconductor device, comprising:
A method of fabricating a semiconductor device, comprising:
Dependencies are inferred from the claim text.