US 11,386,970 B2Granted

Method for programming a memory system

AssigneeYangtze Memory Technologies Co., Ltd.

InventorsHaibo Li, Man Lung Mui

Life of this patent

Estimating the term…

Loading patent…

Abstract

A memory system includes a plurality of memory cells, and the memory cells are multiple-level cells. The memory system performs program operations to program the memory cells. After each program operation, at least one threshold voltage test is performed to determine if threshold voltages of the memory cells are greater than the verification voltage. When the threshold voltage of a first memory cell is determined to be greater than a first verification voltage, the first memory cell will be inhibited from being programmed during the next program operation. When the threshold voltage of a second memory cell is determined to newly become greater than a second verification voltage, where the second verification voltage is greater than the first verification voltage, the second memory cell will be programmed again during the next program operation.

Claims6

Dependent claims

A method for programming a memory system, the memory system comprising a plurality of memory cells, the method comprising:

performing a plurality of program operations to program the plurality of memory cells;
after each of the plurality of program operations, performing at least one threshold voltage test to determine if threshold voltages of the plurality of memory cells are greater than at least one verification voltage;
when a threshold voltage of a first memory cell is determined to be greater than a first verification voltage, inhibiting the first memory cell from being programmed during a next program operation;
performing a threshold voltage test corresponding to a target programming state of the plurality of memory cells while number of program operations in the target programming state is less than a predetermined number of times, the target programming state being a programming state greater than a minimum programming state;
and
while the number of program operations in the target programming state is less than the predetermined number of times, after performing the threshold voltage test corresponding to the target programming state of the plurality of memory cells, increasing a verification voltage of a following programming state following the target programming state to be higher than a target threshold voltage of the following programming state, the increased verification voltage being used in a following threshold voltage test;
wherein the plurality of memory cells are multiple-level cells (MLC).

4 more elements

A method for programming a memory system, the memory system comprising a plurality of memory cells, the method comprising:

performing a plurality of program operations to program the plurality of memory cells;
after each of the plurality of program operations, performing at least one threshold voltage test to determine if threshold voltages of the plurality of memory cells are greater than at least one verification voltage;
when a threshold voltage of a first memory cell is determined to be greater than a first verification voltage, inhibiting the first memory cell from being programmed during a next program operation;
and
performing a threshold voltage test corresponding to a target programming state of the plurality of memory cells while number of program operations in the target programming state is less than a predetermined number of times, the target programming state being a programming state greater than a minimum programming state;
and
after performing the threshold voltage test corresponding to the target programming state of the plurality of memory cells, increasing a verification voltage of a following programming state following the target programming state to be higher than a target threshold voltage of the following programming state, the increased verification voltage being used in a following threshold voltage test;
wherein the plurality of memory cells are multiple-level cells (MLC).

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/924,133Filed 8 Jul 2020 · division
Priority: 20 Feb 2019
Published: US 2020/0265904 A129 Oct 2020
Granted: 12 Jul 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 16/3486
Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing: circuits or methods to prevent overprogramming of…
G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
G11C 16/3459
Arrangements for verifying correct programming or for detecting overprogrammed cells: circuits or methods to verify correct programming of…

Family

PCT/CN2019/075549Parent of this continuation · filed 20 Feb 2019
Application16/371,130Parent of this division · filed 1 Apr 2019
US 2020/0342947 A1Pre-grant publication · published 29 Oct 2020
US 11,037,642 B2Parent of this division
Application16/371,130Parent of this continuation
US 2020/0265904 A1Published application
US 11,386,970 B2This patent

From the US filing history. Foreign family members aren’t listed.