Memory apparatus and method of operation using plane dependent ramp rate and timing control for program operation

A controller in communication with a memory apparatus including a plurality of memory cells connected to word lines and bit lines and arranged in a plurality of planes, the controller configured to:

• determine whether a program operation of the plurality of memory cells involves all of the plurality of planes;
• and
• in response to the program operation of the plurality of memory cells not involving all of the plurality of planes, instruct the memory apparatus to adjust at least one of a bit line ramp rate of a bit line voltage applied to the bit lines and a word line ramp rate of at least one word line voltage applied to the word lines during the program operation of the plurality of memory cells based on a quantity of the plurality of planes associated with the plurality of memory cells being program-verified in the program operation.

A method of operating a memory apparatus including a plurality of memory cells connected to word lines and bit lines and arranged in a plurality of planes, the method comprising the steps of:

• determining whether a program operation of the plurality of memory cells involves all of the plurality of planes;
• and
• adjusting at least one of a bit line ramp rate of a bit line voltage applied to the bit lines and a word line ramp rate of at least one word line voltage applied to the word lines during the program operation of the plurality of memory cells based on a quantity of the plurality of planes associated with the plurality of memory cells being program-verified in the program operation in response to the program operation of the plurality of memory cells not involving all of the plurality of planes.