Voltage generator and memory device including the same

A voltage generator, comprising:

• a band-gap reference circuit configured to generate a bias voltage;
• a low-dropout regulator (LDO) regulator configured to generate a first power voltage and a second power voltage, based on the bias voltage;
• and
• a reference voltage generator including a first resistor chain including first resistors connected between the first power voltage and the second power voltage, a second resistor chain including second resistors connected between the first power voltage and the second power voltage, and a plurality of decoders connected to at least one of the first resistor chain and the second resistor chain and configured to output reference voltages,
• wherein the reference voltage generator is configured such that,
• in a standby mode, a first standby current flows in the first resistor chain, and a second standby current, which is lower than the first standby current, flows in the second resistor chain, and
• in an active mode, a first operating current flows in the first resistor chain and a second operating current, which is larger than the first operating current, flows in the second resistor chain.

A memory device, comprising:

• a memory cell area having first pads;
• and
• a peripheral circuit area having second pads, and connected to the memory cell area by coupling the first pads and the second pads in a first direction,
• wherein the peripheral circuit area further includes a row decoder connected to memory cells in the memory cell area by word lines and select lines, a page buffer connected to the memory cells by bit lines, a control logic configured to control the row decoder and the page buffer, and a voltage generator configured to output reference voltages in response to a control command of the control logic,
• wherein the voltage generator includes a first resistor chain having first resistors connected to each other in series and a first power switch, a second resistor chain having second resistors connected to each other in series and a second power switch, and a plurality of decoders connected to first intermediate nodes between the first resistors and second intermediate nodes between the second resistors, and
• wherein the plurality of decoders are connected to each other in parallel and are configured to simultaneously output the reference voltages different from each other.