Access operations in capacitive sense NAND memory

A memory, comprising:

• a plurality of non-volatile memory cells comprising a plurality of strings of series-connected non-volatile memory cells;
• a plurality of first data lines;
• a second data line;
• a source;
• a plurality of pass gates connected in series between the second data line and the source, wherein each pass gate of the plurality of pass gates comprises a first channel, a second channel, a first control gate capacitively coupled to its first channel, and a second control gate capacitively coupled to its second channel;
• a plurality of capacitances, wherein, for each capacitance of the plurality of capacitances, an electrode of that capacitance is selectively connected to a respective string of series-connected non-volatile memory cells of the plurality of strings of series-connected non-volatile memory cells, and the electrode of that capacitance is capacitively coupled to the first channel of a respective pass gate of the plurality of pass gates;
• and
• a controller for access of the non-volatile memory cell, wherein the controller, during a sense operation of the memory, is configured to cause the memory to:
• for each capacitance of the plurality of capacitances, increase a voltage level of the electrode of that capacitance;
• for each capacitance of the plurality of capacitances, selectively discharge the voltage level of the electrode of that capacitance through its respective string of series-connected non-volatile memory cells responsive to a data state stored in a particular non-volatile memory cell of its respective string of series-connected non-volatile memory cells;
• and
• for each capacitance of the plurality of capacitances, determine whether the first control gate of the respective pass gate of that capacitance is activated in response to a remaining voltage level of the electrode of that capacitance.

A memory, comprising:

• a plurality of first data lines;
• a second data line;
• a source;
• a plurality of pass gates connected in series between the second data line and the source, wherein each pass gate of the plurality of pass gates comprises a first channel, a second channel, a first control gate capacitively coupled to its first channel, and a second control gate capacitively coupled to its second channel;
• a plurality of unit column structures, wherein each unit column structure of the plurality of unit column structures comprises a respective string of series-connected non-volatile memory cells, and wherein each unit column structure of the plurality of unit column structures is capacitively coupled to the first channel of a respective pass gate of the plurality of pass gates;
• a plurality of access lines, wherein each access line of the plurality of access lines is connected to a control gate of a respective non-volatile memory cell of the respective string of series-connected non-volatile memory cells for each unit column structure of the plurality of unit column structures;
• and
• a controller for access of the respective string of memory cells for each unit column structure of the plurality of unit column structures, wherein the controller, during a programming operation of the memory, is configured to cause the memory to:
• apply a first voltage level to each first data line of a first subset of first data lines of the plurality of first data lines, and apply a second voltage level, different than the first voltage level, to each first data line of a second subset of first data lines of the plurality of first data lines;
• connect the respective string of series-connected non-volatile memory cells for each unit column structure of the plurality of unit column structures that is selectively connected to a respective first data line of the first subset of data lines to its respective first data line of the first subset of data lines;
• isolate the respective string of series-connected non-volatile memory cells for each unit column structure of the plurality of unit column structures that is selectively connected to a respective first data line of the second subset of data lines from its respective first data line of the second subset of data lines;
• increase a voltage level applied to each access line of the plurality of access line to a pass voltage level;
• and
• increase the voltage level applied to a particular access line of the plurality of access line to a programming voltage level from the pass voltage level while maintaining the voltage level applied to each remaining access line of the plurality of access lines.