Memory device, memory system including the memory device, and operating method of the memory system

A memory system comprising:

• a memory device including a plurality of memory blocks and a peripheral circuit for performing a normal read operation and a read retry operation on a selected memory block among the plurality of memory blocks;
• and
• a controller configured to control the memory device to perform the normal read operation in response to a request received from a host, and control the memory device to perform the read retry operation according to a number of error bits of read data received from the memory device,
• wherein, in the read retry operation, the controller controls the memory device to perform the read retry operation on all of memory cells included in the selected memory block and programmed to a plurality of program states, and in the read retry operation, to apply a plurality of read voltages respectively corresponding to the plurality of program states to the all of the memory cells and to skip an operation for applying a read voltage corresponding to at least one specific program state among the plurality of program states,
• wherein the at least one specific program state has a stable threshold voltage distribution according to lapse of time in a range of −0.5 V to 1.0 V when the selected memory block is programmed using a triple level cell (TLC) scheme, and in a range of −1.5 V to 1.0 V or −1.0 V to 1.5 V when the selected memory block is programmed using a quad level cell (QLC) scheme.

A method for operating a memory system, the method comprising:

• reading a read retry table stored in a memory device in a power-on operation;
• performing a normal read operation on a selected memory block among a plurality of memory blocks included in the memory device;
• determining whether an error correction operation is to be performed according to a number of error bits in data read in performing the normal read operation;
• setting at least one new read voltage, when it is determined that the error correction operation is not to be performed;
• and
• performing a read retry operation on the selected memory block using the at least one new read voltage,
• wherein the at least one new read voltage corresponds to program states other than at least one program state among a plurality of program states included in a specific threshold voltage region among a plurality of program states of the selected memory block, and
• wherein the performing of the read retry operation comprises:
• applying new read voltages respectively corresponding to program states other than at least one specific program state among the plurality of program states to all of memory cells included in the selected memory block;
• and
• skipping an operation for applying a new read voltage corresponding to the at least one specific program state to the all of the memory cells,
• wherein the at least one specific program state has a stable threshold voltage distribution according to lapse of time in a range of −0.5 V to 1.0 V when the selected memory block is programmed using a triple level cell (TLC) scheme, and in a range of −1.5 V to 1.0 V or −1.0 V to 1.5 V when the selected memory block is programmed using a quad level cell (QLC) scheme.