Systems and methods involving hardware-based reset of unresponsive memory devices
AssigneeMicron Technology, Inc.
InventorsVipul Patel, Theodore Pekny
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Abstract
Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state.
Claims20
A memory device comprising:
- at least one memory array;
- input/output circuitry coupled to the at least one memory array and configured to read from and write to the at least one memory array;
- control circuitry coupled to the at least one memory array and the input/output circuitry and configured to control operation of the memory device, the control circuitry comprising an output providing a busy signal indicating that the memory device is busy;
- and
- reset circuitry comprising timeout circuitry and logic, coupled to the control circuitry and configured to reset the memory device, wherein the reset circuitry is configured to generate a global reset signal in response to a determination that the timeout circuit has been activated for longer than a predetermined period, wherein the predetermined period is set as being greater than the longer of:
- a first time that a write protect signal is maintained active to perform the reset of an erase or program operation;
- or
- a second time, determined for the memory device, that the busy signal is allowed to be active indicating a busy state before the memory device requires reset;
- wherein the timeout circuitry is configured to activate in response to the write protect signal and in response to the busy signal, the write protect signal configured to reset the erase or program operation of the memory device;
- and
- wherein the global reset signal is configured to power-down and power-up the control circuitry to reset the memory device.
A memory device comprising:
- at least one memory array;
- input/output circuitry coupled to the at least one memory array and configured to read from and write to the at least one memory array;
- control circuitry coupled to the at least one memory array and the input/output circuitry and configured to control operation of the memory device, the control circuitry comprising an output providing a busy signal indicating that the memory device is busy;
- and
- reset circuitry coupled to the control circuitry and configured to reset the memory device, the reset circuitry comprising timeout circuitry, wherein the reset circuitry is configured to generate a global reset signal in response to a determination that the timeout circuit has been activated for longer than a predetermined period;
- wherein the timeout circuitry is configured to activate in response to a write protect signal and the busy signal;
- and
- wherein the global reset signal is configured to reset the memory device.
A method comprising:
- receiving, in a memory device, a write protect signal;
- activating, in response to the write protect signal and in response to a busy signal from a controller of the memory device, a timeout circuit;
- determining that the timeout circuit has been activated for longer than a predetermined period;
- generating, by the timeout circuit, a reset signal in response to determining that the timeout circuit has been activated for longer than the predetermined period;
- and
- powering-down and powering-up the controller of the memory device in response to the reset signal.
Dependencies are inferred from the claim text.