EEPROM memory device and corresponding method

An electrically-erasable programmable read-only memory device comprising:

• a matrix memory plane arranged in rows and columns of memory words, each memory word comprising several bytes of memory cells;
• write circuitry configured to perform a write operation in response to receiving a command for writing at least one selected byte in at least one selected memory word of the matrix memory plane, wherein the write operation comprises an erase cycle followed by a programming cycle, wherein the write circuitry is configured for generating:
• during the erase cycle:
• an erase voltage in memory cells of all bytes of the at least one selected memory word, wherein the erase voltage is configured to cause the memory cells of the at least one selected memory word to be erased, and
• an erase inhibit potential configured relative to the erase voltage for preventing erasing of memory cells of non-selected bytes of the at least one selected memory word;
• and
• during the programming cycle, a programming voltage in previously programmed memory cells of at least one non-selected byte of the at least one selected memory word;
• and
• read circuitry configured for:
• reading, during the write operation and prior to the erase cycle, data contained in the memory cells of the at least one non-selected byte of the at least one selected memory word, and
• reading previous data and measuring a quantification of programming of previously programmed memory cells in the at least one non-selected byte of the at least one selected memory word;
• and
• wherein the write circuitry is further configured for generating the programming voltage in the previously programmed memory cells of the at least one non-selected byte of the at least one selected memory word, in response to the quantification of the programming measured in these memory cells being less than a margin taken on a nominal value of the quantification of the programming.

A method for writing in an electrically-erasable programmable read-only memory comprising a matrix memory plane arranged in rows and columns of memory words each comprising several bytes of memory cells, the method comprising:

• receiving a command for writing at least one selected byte in at least one selected memory word of the matrix memory plane;
• and
• in response to receiving the command, performing a write operation comprising:
• prior to an erase cycle, reading data contained in at least one non-selected byte of the at least one selected memory word;
• the erase cycle, comprising:
• generating an erase voltage in memory cells of all bytes of the at least one selected memory word, the erase voltage being able to cause the memory cells to be erased, and
• generating an erase inhibit potential configured with respect to the erase voltage for preventing erasing of memory cells of non-selected bytes of the at least one selected memory word;
• and
• a programming cycle comprising generating a programming voltage in previously programmed memory cells of the at least one non-selected byte of the at least one selected memory word,
• the erase inhibit potential resulting, with respect to the erase voltage, in an erase alteration in the memory cells of the non-selected bytes of the at least one selected memory word, causing an incomplete erasing of these memory cells, in order to prevent complete erasing of the memory cells.