Centralized fixed rate serializer and deserializer for bad column management in non-volatile memory

An apparatus, comprising:

• an array of non-volatile memory cells formed along a plurality of word lines and a plurality of columns, the columns being divided into a plurality of M+N divisions, each of the M+N divisions formed of a plurality of contiguous columns, wherein the word lines span the columns of the array, M is an integer greater than 1, and N is an integer greater than or equal to 1;
• M+N sets of data latches, each set of data latches connectable to the columns of a corresponding one of the M+N divisions and each configured to hold data being transferred between the set of data latches and the corresponding division;
• an input/output circuit configured to transfer data on and off of the apparatus serially;
• a serializer/deserializer circuit connected to the input/output circuit and selectively connectable to M sets of the M+N sets of data latches and configured to transfer data between a selected M sets of the M+N sets of data latches and the input/output circuit;
• and
• one or more control circuits connected to the M+N sets of data latches and the serializer/deserializer circuit, the one or more control circuits configured to transfer data between the input/output circuit and the sets of data latches by converting a first M sets of data between a serial format and a parallel format by accessing a first selected M sets of the M+N sets of data latches concurrently by the serializer/deserializer circuit and to select which of the first M sets of data is transferred first when the first M sets of data are in a serial format at the input/output circuit.