Semiconductor memory device
AssigneeKioxia Corporation
InventorNorichika Asaoka
Life of this patent
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Abstract
A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address.
Claims10
A semiconductor memory device comprising:
- a plurality of planes including a first plane and a second plane, each of the planes including:
- a memory cell array including a plurality of blocks, each of the blocks having a plurality of memory cells;
- a row decoder including a plurality of block decoders provided correspondingly with the blocks, each of the block decoders having a level shifter, a first decode circuit, and a register;
- and
- a sense amplifier module;
- a first plane selection line connected to the first decode circuits in the first plane;
- a second plane selection line connected to the first decode circuits in the second plane;
- an address designation line connected to the registers in the first plane and the registers in the second plane;
- and
- a set line connected to the registers in the first plane and the registers in the second plane.
Dependencies are inferred from the claim text.